公开(公告)号：US06819730B2

公开(公告)日：2004-11-16

申请号：US10205750

申请日：2002-07-26

申请人： Tingbo He

发明人： Tingbo He

IPC分类号： H03D324

CPC分类号： H04J3/076 ,  H03L7/085 ,  H03L7/0994

摘要： A filtering method for digital phase lock loop, comprises defining an ideal phase difference value between an input clock and a local recovery clock; calculating a phase difference between the input clock and the local recovery clock by a subtractor; and comparing the phase difference with the ideal phase difference value to adjust the local recovery clock to keep its phase difference stable in the ideal phase difference value. When adjusting the local recovery clock, taking the ideal phase difference value as a center, the phase difference is divided into different segments. For segments where the ideal phase difference value is located, the local recovery clock follows the phase difference with a minimum changing rate; and for segments farther apart from the ideal phase difference value, the local recovery clock follows the phase difference with a faster changing rate. The invention concerns non-error code and vibration minimization at the same time, so vibration tolerance is better raised, vibration transfer characteristics are very good, and net output vibration indicators at low band and high band parts is improved.

摘要翻译： 一种用于数字锁相环的滤波方法，包括：在输入时钟和本地恢复时钟之间定义理想的相位差值; 通过减法器计算输入时钟和本地恢复时钟之间的相位差; 并将相位差与理想相位差进行比较，调整局部恢复时钟，使其相位差在理想的相位差中保持稳定。 调整本地恢复时钟时，以理想的相位差为中心，将相位差分成不同的段。 对于理想相位差位置的区段，局部恢复时钟以最小变化率跟随相位差; 并且对于远离理想相位差值的段，局部恢复时钟以更快的变化率遵循相位差。 本发明同时涉及无错误代码和振动最小化，因此振动耐受性更好，振动传递特性非常好，提高了低频带和高频带部分的净输出振动指标。

公开(公告)号：US06788754B1

公开(公告)日：2004-09-07

申请号：US09686111

申请日：2000-10-10

申请人： Steven F Liepe

发明人： Steven F Liepe

IPC分类号： H03D324

CPC分类号： H03L7/0812 ,  G06F1/10 ,  H03K5/15013 ,  H03L7/07

摘要： The present invention relates to a system and method for adaptively adjusting delays along selected signal paths in order to equalize the signal delays at various distributed points within an integrated circuit. Where a signal traverses an initial outgoing path and a return path, delay elements disposed in each of the paths may be adjusted in order to set the entirety of the delay of the signal having traveled the entire signal trajectory equal to the delay present in a deliberately introduced delay element of known value. Alternatively, the inventive mechanism may control a selected one of two (or other plurality of) delay elements so as to automatically and adaptively adjust the delay value of the selected delay element so as to equalize the signal delay incurred along two or more signal paths.

摘要翻译： 本发明涉及一种用于自适应地调整所选择的信号路径上的延迟以便均衡集成电路内的各个分布点处的信号延迟的系统和方法。 在信号穿过初始输出路径和返回路径的情况下，可以调整设置在每个路径中的延迟元件，以便将已经行进的信号的整个延迟的整体设置为等于故意存在的延迟 引入已知值的延迟元件。 或者，本发明的机构可以控制两个（或其它多个）延迟元件中的所选择的一个，以便自动和自适应地调整所选择的延迟元件的延迟值，以便均衡沿两个或更多个信号路径引起的信号延迟。

公开(公告)号：US06775345B1

公开(公告)日：2004-08-10

申请号：US09475497

申请日：1999-12-30

申请人： Hongjiang Song

发明人： Hongjiang Song

IPC分类号： H03D324

CPC分类号： H04L7/0338 ,  H03L7/0814 ,  H04L7/0041

摘要： An apparatus including a sampling circuit to generate sampling clocks from a local clock and the sampling clocks to sample incoming data and a quarter clock, a phase detector to detect a phase difference between a data transition in sampled data and the local clock, and a delay line adapted to delay the sampled data by the detected phase difference.

摘要翻译： 一种包括采样电路的装置，用于从本地时钟产生采样时钟，采样时钟采样输入数据和四分之一时钟;相位检测器，用于检测采样数据中的数据转换与本地时钟之间的相位差;以及延迟 线路适于通过检测到的相位差来延迟采样数据。

公开(公告)号：US06757350B1

公开(公告)日：2004-06-29

申请号：US09332204

申请日：1999-06-12

申请人： Jay A. Chesavage

发明人： Jay A. Chesavage

IPC分类号： H03D324

CPC分类号： G06F11/1604 ,  G06F11/1608 ,  H03L7/07 ,  H03L7/087 ,  H03L7/093

摘要： A system for the generation and distribution a plurality of coherently phased system clocks comprises a local clock generator and a plurality of remote clock generators. Each clock generator has a local input and a plurality of remote inputs coupled to a plurality of phase detectors, a cost function coupled to each phase detector and producing a control output, and the control output coupled to a voltage controlled oscillator and producing a local clock output, which is distributed to each local and remote clock generator. The cost function comprises a linear or non-linear combination of phase error and offset. A clock selection circuit comprises a control input which changes a propagation time away from the coherently phased edges of the system clock, thereby selecting a system clock in a glitch-free manner.

摘要翻译： 用于生成和分发多个相干相位系统时钟的系统包括本地时钟发生器和多个远程时钟发生器。 每个时钟发生器具有耦合到多个相位检测器的本地输入和多个远程输入，耦合到每个相位检测器并产生控制输出的成本函数，以及耦合到压控振荡器并产生本地时钟的控制输出 输出，分配给每个本地和远程时钟发生器。 成本函数包括相位误差和偏移的线性或非线性组合。 时钟选择电路包括控制输入，该控制输入改变远离系统时钟的相干相位边缘的传播时间，从而以无毛刺的方式选择系统时钟。

公开(公告)号：US06741668B1

公开(公告)日：2004-05-25

申请号：US09593932

申请日：2000-06-15

申请人： Satoshi Nakamura

发明人： Satoshi Nakamura

IPC分类号： H03D324

CPC分类号： H03L7/0891 ,  H03L7/087 ,  H04L7/033

摘要： A clock recovery circuit provides a reference clock signal and a plurality of clock pulses with phases different from the reference clock signal, and has an edge detecting circuit for detecting positions of edges of inputted serial random data. A detected edge selecting circuit selects whether the edges of the inputted serial random data are rising edges or falling edges of the reference clock signal. An edge position correcting circuit assures that the number of the selected edges is equal to the number of the edges of the inputted serial random data. Phase frequency detectors output pulses of a pulse width in proportion to the phase difference between the inputted serial random data and the reference clock signal.

摘要翻译： 时钟恢复电路提供参考时钟信号和具有不同于参考时钟信号的相位的多个时钟脉冲，并且具有用于检测输入的串行随机数据的边沿位置的边缘检测电路。 检测到的边缘选择电路选择输入的串行随机数据的边缘是否是参考时钟信号的上升沿或下降沿。 边缘位置校正电路确保所选择的边缘的数量等于输入的串行随机数据的边缘的数量。 相位频率检测器输出与所输入的串行随机数据和参考时钟信号之间的相位差成比例的脉冲宽度的脉冲。

公开(公告)号：US06728327B1

公开(公告)日：2004-04-27

申请号：US09477658

申请日：2000-01-05

申请人： Brian Schoner

发明人： Brian Schoner

IPC分类号： H03D324

CPC分类号： H03L7/07 ,  H03B21/02 ,  H03B2202/07

摘要： A circuit combines the outputs of two or more phase locked loops to reduce jitter to a level below that of an individual phase locked loop. A digital version of the circuit uses a majority function to determine the median value of the phase locked loops. An analog version of the circuit averages the outputs of the phase locked loops.

摘要翻译： 一个电路组合两个或多个锁相环路的输出，以将抖动降低到低于单个锁相环路径的电平。 电路的数字版本使用多数函数来确定锁相环的中值。 电路的模拟版本平均了锁相环的输出。

公开(公告)号：US06717998B2

公开(公告)日：2004-04-06

申请号：US09733949

申请日：2000-12-12

申请人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

发明人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

IPC分类号： H03D324

CPC分类号： H03L7/1976

摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

公开(公告)号：US06680992B1

公开(公告)日：2004-01-20

申请号：US09383099

申请日：1999-08-25

申请人： Takenori Morikawa ,  Masaaki Soda ,  Satomi Shioiri

发明人： Takenori Morikawa ,  Masaaki Soda ,  Satomi Shioiri

IPC分类号： H03D324

CPC分类号： H03D13/003

摘要： A clock identification and reproduction circuit which synchronizes a clock signal with an input signal includes a voltage controlled generator for generating a clock signal, a phase comparator for detecting a phase difference between an input signal and a clock signal to generate a phase difference signal according to the phase difference, and a filter for synchronizing a clock signal of the voltage controlled generator in response to a phase difference signal, in which the phase comparator generates a phase difference signal when a specific pulse waveform of a pulse of an input signal changes.

摘要翻译： 将时钟信号与输入信号同步的时钟识别和再现电路包括用于产生时钟信号的电压控制发生器，用于检测输入信号和时钟信号之间的相位差的相位比较器，以产生根据 所述相位差和用于响应于相位差信号使所述受压发生器的时钟信号同步的滤波器，其中当输入信号的脉冲的特定脉冲波形改变时相位比较器产生相位差信号。

公开(公告)号：US06671343B1

公开(公告)日：2003-12-30

申请号：US09479697

申请日：2000-01-07

申请人： Tsugio Ito

发明人： Tsugio Ito

IPC分类号： H03D324

CPC分类号： H04J3/0664 ,  H04J3/0632 ,  H04L12/40091

摘要： A data clock generator, a data clock generating method and a storage medium therefor are provided, which make it possible to reduce burden on a PLL circuit and substantially reduce jitter in the generated data clock signal, as well as achieve a sufficiently wide lock range of the PLL circuit. Data packets are supplied, which include at least a plurality of data samples and time stamps which are smaller in number than the number of the plurality of data samples. Time samples are generated, respectively, for the data samples from the time stamps of the supplied data packets. A PLL circuit generates a data clock signal based on the time samples for the respective data samples.

摘要翻译： 提供了一种数据时钟发生器，数据时钟产生方法及其存储介质，这使得可以减少PLL电路的负担，并且显着减少所产生的数据时钟信号中的抖动，并且实现足够宽的锁定范围 PLL电路。 提供数据分组，其包括数量少于多个数据样本的数量的至少多个数据样本和时间戳。 分别从提供的数据包的时间戳中为数据样本生成时间样本。 PLL电路基于各个数据采样的时间采样产生数据时钟信号。

公开(公告)号：US06639933B2

公开(公告)日：2003-10-28

申请号：US09993764

申请日：2001-11-27

申请人： Taizo Yamawaki ,  Masaru Kokubo ,  Tomio Furuya ,  Kazuo Watanabe ,  Julian Hildersley

发明人： Taizo Yamawaki ,  Masaru Kokubo ,  Tomio Furuya ,  Kazuo Watanabe ,  Julian Hildersley

IPC分类号： H03D324

CPC分类号： H03L7/085 ,  H03L7/10 ,  H03L7/183 ,  H03L2207/12 ,  H04B1/403 ,  H04B1/408

摘要： A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency, and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal, a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter, the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.