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公开(公告)号：US06717998B2
公开(公告)日：2004-04-06
申请号：US09733949
申请日：2000-12-12
IPC分类号： H03D324
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
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公开(公告)号：US07110486B2
公开(公告)日：2006-09-19
申请号：US11333245
申请日：2006-01-18
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
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公开(公告)号：US07050525B2
公开(公告)日：2006-05-23
申请号：US10728863
申请日：2003-12-08
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
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4.发明申请公开(公告)号：US20060115036A1
公开(公告)日：2006-06-01
申请号：US11333245
申请日：2006-01-18
IPC分类号： H03D3/24
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
摘要翻译： 包括PLL电路的频率合成器装置的分数部分控制电路是用于控制与PLL电路的可变分频器分频的分数部分的多n-Δ级Δ-Σ调制器电路。 加法器将分数部分的数据与来自乘法器的输出数据相加，并将结果数据通过二阶积分器输出到量化器。 量化器用量化步长量化输入数据，并通过反馈电路将量化的数据输出到乘法器。 量化数据用作受控分数部分的数据。 乘法器将来自反馈电路的数据乘以量化步长，并将结果数据输出到加法器。 分数部分控制电路周期性地改变分数部分的数据，从而根据周期的平均值设置来自VCO的输出信号的频率。
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5.发明授权PLL oscillation circuit, polar transmitting circuit, and communication device 失效PLL振荡电路，极性发射电路和通信装置公开(公告)号：US07839230B2
公开(公告)日：2010-11-23
申请号：US12469252
申请日：2009-05-20
IPC分类号： H03L5/00
CPC分类号： H03L7/099 , H03C3/04 , H03C3/0925 , H03C3/0933 , H03C5/00 , H03L5/00
摘要： Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.
摘要翻译： 提供了一种PLL振荡电路，其可以降低VCO 101的调制灵敏度的可变性，并以高精度快速获得期望的输出幅度。 振幅检测器103检测VCO 101的输出幅度。振幅控制器105控制可变电流源109的电流值，使振幅检测器103检测到的VCO 101的输出幅度为期望幅度。 LPF 108连接在振幅控制器105和可变电流源109之间。开关107连接或断开振幅控制器105和可变电流源109之间的LPF108。振幅控制器105连接到可变电流源109 通过LPF 108或切换开关107。
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公开(公告)号：US08633101B2
公开(公告)日：2014-01-21
申请号：US13499652
申请日：2010-09-02
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/44 , H01L21/302 , H01L21/461 , H01L21/31
CPC分类号： H01L29/452 , H01L21/28575 , H01L29/2003 , H01L33/0095 , H01L33/32 , H01L33/40
摘要： A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.
摘要翻译： 提供了包括对氮化物半导体具有低接触电阻的电极的半导体器件的制造方法。 制造方法包括在氮化物半导体层上形成含有碳的含碳层的含碳层形成工序和在含碳层上形成含有钛的含钛层的含钛层形成工序。 在含钛层和氮化物半导体层之间形成TiN和TiC的完全固溶Ti（C，N）层。 结果，含钛层在其间的整个边界处与氮化物半导体层欧姆接触。
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公开(公告)号：US08508303B2
公开(公告)日：2013-08-13
申请号：US13256748
申请日：2010-02-05
申请人： Masakatsu Maeda
发明人： Masakatsu Maeda
IPC分类号： H03L7/099
CPC分类号： H03L7/107 , H03L7/093 , H03L7/099 , H03L7/1075 , H03L2207/06 , H03L2207/50
摘要： A digital FLL/PLL is provided which is capable of converging an oscillation frequency from a VCO to a desired frequency at a high speed even without setting a damping factor corresponding to each VCO gain. A digital FLL/PLL of the present invention includes: a comparator for comparing a channel signal to a loopback signal having an oscillation frequency to generate a signal error; a digital loop filter for generating a control voltage that determines the oscillation frequency, on the basis of the signal error; a VCO for controlling an oscillation frequency on the basis of the control voltage; a loopback path through which the oscillation frequency generated by the VCO is outputted as the loopback signal to the comparator; and a control section for monitoring the signal error, and controlling the digital loop filter such that the oscillation frequency of the VCO becomes a stationary state, when detecting that the signal error meets a predetermined condition after the channel signal is switched.
摘要翻译： 提供了一种数字FLL / PLL，其能够以高速将VCO的振荡频率收敛到期望的频率，而不设置对应于每个VCO增益的阻尼因子。 本发明的数字FLL / PLL包括：比较器，用于将信道信号与具有振荡频率的环回信号进行比较以产生信号误差; 数字环路滤波器，用于基于信号误差产生确定振荡频率的控制电压; 用于基于所述控制电压来控制振荡频率的VCO; 由VCO产生的振荡频率作为环回信号输出到比较器的环回路径; 以及用于监视信号误差的控制部分，并且当在信道信号被切换之后检测到信号误差满足预定条件时，控制数字环路滤波器使得VCO的振荡频率变为静止状态。
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公开(公告)号：US08477870B2
公开(公告)日：2013-07-02
申请号：US13380947
申请日：2010-04-09
申请人： Masakatsu Maeda
发明人： Masakatsu Maeda
IPC分类号： H04L27/00
CPC分类号： H03F1/0205 , H03F3/24 , H03F2200/324 , H03F2200/336
摘要： Provided is a transmitter including a polar modulation circuit which adjusts a timing lag between an amplitude component and a phase component more accurately than a conventional art. The polar modulation circuit includes: a first calculator for performing an exclusive OR logical operation between the amplitude component before and after being inputted to the first processing section; a second calculator for performing an exclusive OR logical operation between the phase component before and after being inputted to the second processing section; and a delay fluctuation detection/compensation section for obtaining a delay time of the amplitude component based on an amount of output accumulation of the first calculator; obtaining a delay time of the phase component based on an amount of output accumulation of the second calculator; detecting an amount of delay fluctuation by using the delay times; and adjusting timings of the amplitude component and the phase component.
摘要翻译： 提供了一种发射器，其包括极限调制电路，其比常规技术更准确地调节幅度分量和相位分量之间的定时滞后。 极坐标调制电路包括：第一计算器，用于在输入到第一处理部分之前和之后的幅度分量之间执行异或逻辑运算; 第二计算器，用于在输入到第二处理部分之前和之后的相位分量之间执行异或逻辑运算; 以及延迟波动检测/补偿部分，用于基于第一计算器的输出累积量来获得振幅分量的延迟时间; 基于第二计算器的输出累积量获得相位分量的延迟时间; 通过使用延迟时间检测延迟波动量; 并调整振幅分量和相位分量的定时。
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公开(公告)号：US20120105111A1
公开(公告)日：2012-05-03
申请号：US13380947
申请日：2010-04-09
申请人： Masakatsu Maeda
发明人： Masakatsu Maeda
CPC分类号： H03F1/0205 , H03F3/24 , H03F2200/324 , H03F2200/336
摘要： Provided is a transmitter including a polar modulation circuit which adjusts a timing lag between an amplitude component and a phase component more accurately than a conventional art. The polar modulation circuit includes: an extraction section for extracting an amplitude component and a phase component from an input signal; a first processing section for performing a first signal process on the amplitude component; a second processing section for performing a second signal processing on the phase component; an amplifier for synthesizing an output of the first processing section and an output of the second processing section and amplifying the synthesized outputs; a first calculator for performing an exclusive OR logical operation between the amplitude component before being inputted to the first processing section and the amplitude component after having been inputted to the first processing section; a first accumulation section for accumulating outputs of the first calculator; a second calculator for performing an exclusive OR logical operation between the phase component before being inputted to the second processing section and the phase component after having been inputted to the second processing section; a second accumulation section for accumulating outputs of the second calculator; and a delay fluctuation detection/compensation section for obtaining a delay time of the amplitude component based on an amount of accumulation of the first accumulation section; obtaining a delay time of the phase component based on an amount of accumulation of the second accumulation section; detecting an amount of delay fluctuation by using the delay times; and adjusting timings of the amplitude component and the phase component.
摘要翻译： 提供了一种发射器，其包括极限调制电路，其比常规技术更准确地调节幅度分量和相位分量之间的定时滞后。 极坐标调制电路包括：提取部分，用于从输入信号中提取振幅分量和相位分量; 第一处理部分，用于对振幅分量执行第一信号处理; 第二处理部，对相位成分进行第二信号处理; 用于合成第一处理部分的输出和第二处理部分的输出并放大合成输出的放大器; 第一计算器，用于在输入到第一处理部分之前的幅度分量和已经被输入到第一处理部分之后的幅度分量之间执行异或逻辑运算; 第一累积部分，用于累积第一计算器的输出; 第二计算器，用于在输入到第二处理部分之前的相位分量和被输入到第二处理部分之后的相位分量之间执行异或逻辑运算; 第二累积部分，用于累积第二计算器的输出; 以及延迟波动检测/补偿部分，用于基于第一累积部分的累积量获得振幅分量的延迟时间; 基于第二累积部分的累积量获得相位分量的延迟时间; 通过使用延迟时间检测延迟波动量; 并调整振幅分量和相位分量的定时。
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公开(公告)号：US08138428B2
公开(公告)日：2012-03-20
申请号：US12279073
申请日：2007-02-07
申请人： Masakatsu Maeda , Yasuyuki Yamamoto
发明人： Masakatsu Maeda , Yasuyuki Yamamoto
IPC分类号： H05K1/11
CPC分类号： H01L23/10 , H01L23/15 , H01L24/48 , H01L33/483 , H01L33/56 , H01L33/62 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01004 , H01L2924/01012 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/12042 , H05K1/0306 , H05K3/3447 , H05K3/3452 , H05K2201/09909 , H05K2201/10106 , H05K2201/10303 , Y10T29/49139 , Y10T29/49165 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A metallized ceramics substrate including: a ceramics body; a wiring pattern formed on one surface of the ceramics body; and a lead electrically-connected to the wiring pattern. The ceramics body has a through-hole, the lead penetrates the through-hole and sticks out from another surface of the ceramics body, and the lead is fixed by filling an electroconductive filler between the lead and the through-hole for keeping airtightness. The metallized ceramics substrate does not cause a problem of interlayer peeling and is excellent in airtightness and electric conductivity.
摘要翻译： 一种金属化陶瓷基板，包括：陶瓷体; 形成在陶瓷体的一个表面上的布线图案; 以及电连接到布线图案的引线。 陶瓷体具有通孔，引线穿透通孔并从陶瓷体的另一表面伸出，并且通过在引线和通孔之间填充导电填料来固定引线，以保持气密性。 金属化陶瓷基板不会产生层间剥离的问题，气密性和导电性优异。
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