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公开(公告)号：US20240195399A1
公开(公告)日：2024-06-13
申请号：US18223101
申请日：2023-07-18
发明人： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO , Jae-Woong CHOI
CPC分类号： H03K5/1565 , G06F1/12 , G11C11/4076 , H03K5/131 , H03K5/135 , H03L7/0812 , H03K2005/00058
摘要： Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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公开(公告)号：US11979161B2
公开(公告)日：2024-05-07
申请号：US17828190
申请日：2022-05-31
发明人： Sudipto Chakraborty
IPC分类号： H03K5/131 , H04B7/0452 , H04B7/08 , H04J1/08 , H03K5/00
CPC分类号： H03K5/131 , H04B7/0452 , H04B7/084 , H04J1/08 , H03K2005/00286
摘要： In described examples, a quadrature phase shifter includes digitally programmable phase shifter networks for generating leading and lagging output signals in quadrature. The phase shifter networks include passive components for reactively inducing phase shifts, which need not consume active power. Output currents from the transistors coupled to the phase shifter networks are substantially in quadrature and can be made further accurate by adjusted by a weight function implemented using current steering elements. Example low-loss quadrature phase shifters described herein can be functionally integrated to provide low-power, low-noise up/down mixers, vector modulators and transceiver front-ends for millimeter wavelength (mmwave) communication systems.
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公开(公告)号：US11955976B2
公开(公告)日：2024-04-09
申请号：US17973706
申请日：2022-10-26
发明人： Yao-Chia Liu , Yuan-Sheng Lee
IPC分类号： H03K5/00 , H03K5/131 , H03K5/135 , H03K5/15 , H03K19/173
CPC分类号： H03K5/135 , H03K5/131 , H03K5/15093 , H03K19/1737
摘要： A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.
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公开(公告)号：US20240106425A1
公开(公告)日：2024-03-28
申请号：US18526226
申请日：2023-12-01
CPC分类号： H03K5/14 , H03K5/131 , H03K5/134 , H03K5/2481
摘要： A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.
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公开(公告)号：US11855644B2
公开(公告)日：2023-12-26
申请号：US18155906
申请日：2023-01-18
CPC分类号： H03K5/14 , H03K5/131 , H03K5/134 , H03K5/2481
摘要： A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.
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公开(公告)号：US11742017B2
公开(公告)日：2023-08-29
申请号：US17700346
申请日：2022-03-21
发明人： Yasuo Satoh
IPC分类号： G11C11/4076 , H03L7/081 , H03K5/14 , H03K5/131 , H03K5/00
CPC分类号： G11C11/4076 , H03K5/131 , H03K5/14 , H03L7/0814 , H03L7/0818 , H03K2005/00019 , H03K2005/00241
摘要： Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.
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公开(公告)号：US20230208411A1
公开(公告)日：2023-06-29
申请号：US17561859
申请日：2021-12-24
发明人： David Foley
CPC分类号： H03K5/131 , H03M1/661 , H03K2005/00202
摘要： A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.
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公开(公告)号：US20230064239A1
公开(公告)日：2023-03-02
申请号：US17463981
申请日：2021-09-01
发明人： Ming-ta Hsieh , Taylor Loftsgaarden
摘要： A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.
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9.发明申请公开(公告)号：US20230006545A1
公开(公告)日：2023-01-05
申请号：US17364063
申请日：2021-06-30
摘要： A direct current (DC) to DC (DC-DC) converter includes a comparator configured to set a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL configured increase the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer configured to selectively output a delayed version of the signal pulse; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit configured to adaptively adjust a precision of the DC-DC converter in accordance with a duty cycle of the DC-DC converter and a setpoint of the DC-DC converter.
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公开(公告)号：US20220294436A1
公开(公告)日：2022-09-15
申请号：US17828190
申请日：2022-05-31
发明人： Sudipto Chakraborty
IPC分类号： H03K5/131 , H04J1/08 , H04B7/08 , H04B7/0452
摘要： In described examples, a quadrature phase shifter includes digitally programmable phase shifter networks for generating leading and lagging output signals in quadrature. The phase shifter networks include passive components for reactively inducing phase shifts, which need not consume active power. Output currents from the transistors coupled to the phase shifter networks are substantially in quadrature and can be made further accurate by adjusted by a weight function implemented using current steering elements. Example low-loss quadrature phase shifters described herein can be functionally integrated to provide low-power, low-noise up/down mixers, vector modulators and transceiver front-ends for millimeter wavelength (mmwave) communication systems.
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