公开(公告)号：US06535154B1

公开(公告)日：2003-03-18

申请号：US10008486

申请日：2001-11-05

申请人： Terry L. Sculley

发明人： Terry L. Sculley

IPC分类号： H03M302

CPC分类号： H03M1/0668 ,  H03M1/74 ,  H03M3/464 ,  H03M3/502

摘要： Noise-shaped dynamic element matching in analog-to-digital and digital-to-analog converters is increased in such a way that the number of components increases linearly, rather than exponentially, as the number of bits is increased. A processor generates a plurality of input signals for a plurality of digital delta sigma modulators which, in turn, generate a plurality of control signals for selecting a plurality of weighted converter elements. The processor recursively generates the input signals in such a way that the control signals generated by some of the digital delta sigma modulators include error cancellation components to cancel error components in other control signals.

摘要翻译： 模数转换器和数模转换器中的噪声形状的动态元件匹配以这样的方式增加，即随着位数的增加，分量的数量线性增加而不是指数地增加。 处理器为多个数字Δ-Σ调制器产生多个输入信号，其又产生用于选择多个加权转换器元件的多个控制信号。 处理器以这样的方式递归地产生输入信号，使得由一些数字Δ-Σ调制器产生的控制信号包括消除其它控制信号中的误差分量的误差消除分量。

公开(公告)号：US06646581B1

公开(公告)日：2003-11-11

申请号：US10188784

申请日：2002-07-02

申请人： Yunteng Huang

发明人： Yunteng Huang

IPC分类号： H03M302

CPC分类号： H03M7/3011 ,  H03J2200/10 ,  H03M7/3037

摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

摘要翻译： 示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。 用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。 复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。 每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

公开(公告)号：US06369729B1

公开(公告)日：2002-04-09

申请号：US09415294

申请日：1999-10-08

申请人： Vishnu S. Srinivasan ,  Jason Rhode

发明人： Vishnu S. Srinivasan ,  Jason Rhode

IPC分类号： H03M302

CPC分类号： H03M3/32 ,  H03M3/43 ,  H03M3/452 ,  H03M3/464 ,  H03M3/496

摘要： A technique for shifting a common mode voltage in a modulator comprised of a plurality of differential stages, so that downstream stages can use a lower voltage drive than the first stage of the modulator.

摘要翻译： 一种用于在由多个差分级组成的调制器中移动共模电压的技术，使得下游级可以使用比调制器的第一级更低的电压驱动。

公开(公告)号：US06748025B1

公开(公告)日：2004-06-08

申请号：US09241994

申请日：1999-02-02

申请人： Ronald M. Hickling

发明人： Ronald M. Hickling

IPC分类号： H03M302

CPC分类号： H04B1/0014 ,  H04B1/0039 ,  H04B1/28

摘要： A wireless receiver receives a wireless signal by inverting the polarity of an incoming waveform on every one half clock cycle of a conversion clock to produce a commutated waveform and converting said commutated waveform to a series of representative digital values using a delta-sigma modulator clocked by said conversion clock. In this way, the receiver operates over a large dynamic range and the use of automatic gain control in the front end may be eliminated.

摘要翻译： 无线接收器通过在转换时钟的每半个时钟周期反转输入波形的极性来接收无线信号，以产生换向波形，并使用由Δ-Σ调制器转换所述换向波形到一系列代表数字值 表示转换时钟。 以这种方式，接收器在大的动态范围内工作，并且可以消除在前端使用自动增益控制。

公开(公告)号：US06614375B2

公开(公告)日：2003-09-02

申请号：US10214992

申请日：2002-08-08

申请人： James R. Hochschild

发明人： James R. Hochschild

IPC分类号： H03M302

CPC分类号： H03M3/34 ,  H03M3/356 ,  H03M3/43 ,  H03M3/456

摘要： A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The sigma-delta analog-to-digital converter includes a passive filter circuit connected to receive a differential reference voltage input. The improved differential multiplexer couples to the passive filter circuit to receive the reference voltage signal. This differential multiplexer includes three modes of operation: (1) direct coupling of its differential input to its differential output, (2) cross-coupling of its differential input to its differential output, and (3) setting of the differential output to a fixed voltage to discharge the parasitic capacitance associated its differential output every clock cycle. This last mode of operation eliminates the noise of the reference voltage signal and ultimately the sigma-delta ADC. A sigma-delta integrator receives the differential output from the differential multiplexer. A comparator couples to the output of the sigma-delta integrator to provide a decision signal to the differential multiplexer for enabling and disabling the first and second modes of operation; while a clocking signal fed to the differential multiplexer is responsible for enabling and disabling the third mode of operation.

公开(公告)号：US06570518B2

公开(公告)日：2003-05-27

申请号：US09753581

申请日：2001-01-04

申请人： Thomas A. D. Riley ,  Tadeuse A. Kwasniewski ,  Thierry Lepley

发明人： Thomas A. D. Riley ,  Tadeuse A. Kwasniewski ,  Thierry Lepley

IPC分类号： H03M302

CPC分类号： H03M7/3022 ,  H03M7/3026 ,  H03M7/3028

摘要： A delta sigma modulator which uses at least one quantizer having a dead zone. The dead zone quantizer outputs a zero when its input is within the dead zone range. It outputs a predetermined value if the input is above the dead zone range. If the input is below the dead zone range, the quantizer outputs another predetermined value. Ideally, the quantizer dead zone thresholds are complimentary in that the upper threshold for an input is the positive value of the lower threshold. Also, to save on accumulator bits, the delta sigma modulator selects a predetermined number of most significant bits at different stages.

摘要翻译： 使用至少一个具有死区的量化器的Δ-Σ调制器。 死区量化器在其输入在死区范围内时输出零。 如果输入高于死区范围，则输出预定值。 如果输入低于死区范围，则量化器输出另一个预定值。 理想地，量化器死区阈值是互补的，因为输入的上限阈值是较低阈值的正值。 另外，为了节省累加器位，ΔΣ调制器在不同的阶段选择预定数量的最高有效位。

公开(公告)号：US06552676B1

公开(公告)日：2003-04-22

申请号：US09951707

申请日：2001-09-14

申请人： Patrik Bjorksten ,  Sami Kallioinen ,  Jukka Wallinheimo ,  Tom Ahola

发明人： Patrik Bjorksten ,  Sami Kallioinen ,  Jukka Wallinheimo ,  Tom Ahola

IPC分类号： H03M302

CPC分类号： H03H19/004

摘要： Method and apparatus for reducing power in a switched capacitor circuit. In one embodiment, the power reduction apparatus includes a detector connected to both inputs of an operational amplifier in a switched capacitor circuit, and a controller. The detector monitors the inputs. A voltage corresponding to full settling (i.e. a zero difference between the inputs) is stored. The voltage corresponding to the difference between the inputs is compared to the previous value to determine whether it is within the desired range. The controller is connected to an output signal of the detector. The controller adjusts a bias current of the operational amplifier based on the output signal to as low as possible but just above a value where the comparison falls outside the desired range. The power consumption of the operational amplifier is minimized while a settling time of the operational amplifier is still adequate for maximum performance.

摘要翻译： 用于降低开关电容器电路中功率的方法和装置。 在一个实施例中，功率降低装置包括连接到开关电容器电路中的运算放大器的两个输入端的检测器和控制器。 检测器监控输入。 存储对应于完全稳定的电压（即，输入之间的零差）。 将对应于输入之间的差的电压与先前的值进行比较，以确定其是否在期望的范围内。 控制器连接到检测器的输出信号。 控制器基于输出信号将运算放大器的偏置电流调整到尽可能低的位置，但恰好高于比较值超出所需范围的值。 运算放大器的功耗最小化，而运算放大器的稳定时间仍然足以达到最大性能。

公开(公告)号：US06232901B1

公开(公告)日：2001-05-15

申请号：US09384002

申请日：1999-08-26

申请人： Duane L. Abbey

发明人： Duane L. Abbey

IPC分类号： H03M302

CPC分类号： H03M7/3017 ,  H03M3/396 ,  H03M3/43 ,  H03M3/45 ,  H03M3/454 ,  H03M7/304

摘要： A sigma-delta low-pass/band-pass based modulator for analog-to-digital converters includes at least one or more tunable band-pass filter stages. The filter stages are configured arrays with one or more parallel filter stages arranged as a group, and with one or more groups in cascade. The input signal is provided to all filter stages in the first group, and the outputs of the last group are combined and provided to the output processing elements. The output processing elements provide the signal conversion to the converter output, as well as the inverse conversion of the output signal to form the feedback signal or signals. All filter stages receive a feedback signal from the output processing elements. Each of the tunable band-pass filter stages is independently tunable to a respective predetermined frequency. At least one of the filter stages can be configured to support low-pass operation in conjunction with band-pass operation for increased low-pass signal bandwidth. The modulator can also be configured as digital-to-analog converters or as digital resolution reducers.

摘要翻译： 用于模数转换器的Σ-Δ低通/带通调制器包括至少一个或多个可调谐带通滤波器级。 过滤器级是配置有一个或多个并联过滤器级的阵列，并且具有一个或多个级联的组。 将输入信号提供给第一组中的所有滤波器级，并且将最后一组的输出组合并提供给输出处理元件。 输出处理元件提供到转换器输出的信号转换，以及输出信号的反向转换以形成反馈信号。 所有滤波器级从输出处理元件接收反馈信号。 可调谐带通滤波器级中的每一个独立地可调谐到相应的预定频率。 滤波器级中的至少一个可以被配置为支持带通操作的低通操作，以增加低通信号带宽。 调制器也可以配置为数模转换器或数字分辨率降低器。

公开(公告)号：US06697001B1

公开(公告)日：2004-02-24

申请号：US10324684

申请日：2002-12-19

申请人： Omid Oliaei ,  Matthew R. Miller ,  Patrick L. Rakers

发明人： Omid Oliaei ,  Matthew R. Miller ,  Patrick L. Rakers

IPC分类号： H03M302

CPC分类号： H03M3/356 ,  H03M3/43 ,  H03M3/456

摘要： Systems and methods are described for a continuous-time sigma-delta modulator with discrete time common-mode feedback. The method includes calculating an integrator input signal as a difference between an input signal and a modulation feedback signal, continuous time integrating the integrator input signal to produce an integrator output signal having a common mode voltage, determining the common mode voltage of the integrator output signal using a discrete-time process, determining an integrator feedback signal as a function of the common-mode voltage and feeding back the feedback signal to the integrator in order to maintain the common mode voltage at a substantially constant value, sampling and quantizing the integrator output signal to produce a sigma-delta modulated output signal and converting the sigma-delta modulated output signal from a digital signal to an analog signal, to produce the modulation feedback signal.

摘要翻译： 对具有离散时间共模反馈的连续时间Σ-Δ调制器描述了系统和方法。 该方法包括：计算积分器输入信号作为输入信号和调制反馈信号之间的差值，连续时间积分积分器输入信号以产生具有共模电压的积分器输出信号，确定积分器输出信号的共模电压 使用离散时间过程，确定作为共模电压的函数的积分器反馈信号并将反馈信号反馈到积分器，以便将共模电压保持在基本恒定的值，对积分器输出进行采样和量化 信号以产生Σ-Δ调制输出信号，并将Σ-Δ调制输出信号从数字信号转换成模拟信号，以产生调制反馈信号。

公开(公告)号：US06683550B2

公开(公告)日：2004-01-27

申请号：US10016983

申请日：2001-12-14

申请人： Ayman A. Al-Awadhi

发明人： Ayman A. Al-Awadhi

IPC分类号： H03M302

CPC分类号： H03M1/20 ,  H03M1/145 ,  H03M3/326 ,  H03M3/424 ,  H03M3/46

摘要： A topology for converting an analog input signal at an input port into a corresponding digital output signal at an output port includes a plurality of substantially identical ADC stages. Each ADC stage includes a multi-bit sigma-delta loop having an analog input coupled to the input port and a digital output coupled to a combining circuit. The combining circuit adds the outputs of the ADC stages to generate the digital output signal.

摘要翻译： 用于将输入端口处的模拟输入信号转换为输出端口处的相应数字输出信号的拓扑结构包括多个基本相同的ADC级。 每个ADC级包括具有耦合到输入端口的模拟输入和耦合到组合电路的数字输出的多位Σ-Δ环路。 组合电路将ADC级的输出相加以产生数字输出信号。