公开(公告)号：US20240089634A1

公开(公告)日：2024-03-14

申请号：US17940955

申请日：2022-09-08

申请人： Micron Technology, Inc.

发明人： Poorna Kale

IPC分类号： H04N5/3745 ,  G06N3/08 ,  G06V10/764 ,  G06V10/82 ,  G06V10/94 ,  G11C7/10 ,  G11C11/54

CPC分类号： H04N5/37452 ,  G06N3/08 ,  G06V10/764 ,  G06V10/82 ,  G06V10/945 ,  G11C7/1096 ,  G11C11/54 ,  G06V2201/10

摘要： A method for a digital camera adaptable to monitor a scene to detect a condition of interest to a user. The digital camera can program, in a first mode, first memory cells according to first weight matrices to classify images captured by the digital camera. Second memory cells are programmed in a second mode to store data representative of the images. The digital camera can perform operations of multiplication and accumulation using the first memory cells to compute first classifications of the images. In response to mismatches between the first classifications and second classifications identified by the user for the images, the digital camera can execute instructions to determine second weight matrices and program, in the first mode, third memory cells, according to the second weight matrices for improved capability in detecting the condition represented by image classifications in a predetermined category.

公开(公告)号：US20240086691A1

公开(公告)日：2024-03-14

申请号：US17940845

申请日：2022-09-08

申请人： Micron Technology, Inc.

发明人： Poorna Kale

IPC分类号： H04N5/3745 ,  G06N3/063 ,  H04N5/369 ,  H04N5/378

CPC分类号： H04N5/37452 ,  G06N3/063 ,  H04N5/3698 ,  H04N5/378 ,  H04N5/379

摘要： A method of artificial neural network computations, including: receiving image data having pixel values; generating, from the pixel values, a column of inputs to a set of artificial neurons; identifying a region of memory cells of the integrated circuit device having threshold voltages programmed to represent a weight matrix for the set of artificial neurons; instructing voltage drivers in the integrated circuit device to apply voltages to the region of memory cells according to the column of inputs; obtaining, based on the region of memory cells responsive to the applied voltages, a first column of data from an operation of multiplication and accumulation applied on the weight matrix and the column of inputs; and applying activation functions of the set of artificial neurons to the first column of data to generate a second column of data representative of outputs of the set of artificial neuron.

公开(公告)号：US20240022841A1

公开(公告)日：2024-01-18

申请号：US17951828

申请日：2022-09-23

申请人： SmartSens Technology (HK) Co., Ltd

发明人： Guang Yang ,  Jing Yang ,  Jinjian Hou ,  Guanjing Ren ,  Yaowu Mo

IPC分类号： H04N5/3745 ,  H03M1/34 ,  H03M1/10

CPC分类号： H04N5/37455 ,  H03M1/34 ,  H03M1/1071

摘要： An image sensor array and circuit design and method employing a voltage and current detection circuit capable of quantifying a power signal, grounding signal, internal reference voltage and internal reference current. An image sensor comprising the invented circuit design may be incorporated within a digital camera.

公开(公告)号：US20230336891A1

公开(公告)日：2023-10-19

申请号：US17659045

申请日：2022-04-13

申请人： OMNIVISION TECHNOLOGIES, INC.

发明人： Hiroaki Ebihara ,  Zhenfu Tian ,  Peter Bartkovjak ,  Satoshi Sakurai

IPC分类号： H04N5/3745 ,  H03M1/56 ,  H03M1/12 ,  H03K5/24 ,  H04N17/00 ,  H04N5/378 ,  H04N5/369

CPC分类号： H04N5/37455 ,  H03M1/56 ,  H03M1/1245 ,  H03K5/24 ,  H04N17/002 ,  H04N5/378 ,  H04N5/3698

摘要： A ramp buffer circuit includes a ramp buffer input device having an input coupled to receive a ramp signal. A current monitor is circuit coupled to a power line and the ramp buffer input device to generate a current monitor signal in response to an input current conducted through the ramp buffer input device. A corner bias circuit is coupled to the current monitor circuit to generate an assist bias voltage in response to the current monitor signal. A bias current source is coupled to an output of the ramp buffer input device. An assist current source is coupled to the corner bias circuit and coupled between the output of the ramp buffer input device and ground to conduct an assist current from the output of the ramp buffer input device to ground in response to the assist bias voltage.

公开(公告)号：US11736825B2

公开(公告)日：2023-08-22

申请号：US17863776

申请日：2022-07-13

申请人： Shenzhen Genorivision Technology Co. Ltd.

发明人： Peiyan Cao ,  Yurun Liu

IPC分类号： H04N5/3745 ,  H01L27/146 ,  H04N25/53 ,  H04N25/772

CPC分类号： H04N25/53 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14641 ,  H04N25/772 ,  H01L27/14658

摘要： Disclosed herein is a method of operating a radiation detector, comprising for i=1, . . . , N, during a transfer period (i), electrically connecting pixel (1,i) of pixels (1,j), j=1, . . . , N of the radiation detector to a first signal processing circuit while electrically disconnecting the other N−1 pixels of the pixels (1,j), j=1, . . . , N from the first signal processing circuit; and for i=1, . . . , N, during the transfer period (i), transferring electrical signals from the pixel (1,i) to the first signal processing circuit.

公开(公告)号：US20230262351A1

公开(公告)日：2023-08-17

申请号：US17671609

申请日：2022-02-15

申请人： Novatek Microelectronics Corp.

发明人： Wen-Shen Wuen ,  Shen-Fu Tsai ,  Cho-Hsuan Jhang

IPC分类号： H04N5/351 ,  H04N5/3745 ,  H04N5/378 ,  H04N5/369

CPC分类号： H04N5/351 ,  H04N5/37452 ,  H04N5/378 ,  H04N5/379

摘要： An image sensor, including a photosensitive pixel array, a storage element, and a displacement processing element, is provided. The photosensitive pixel array includes a photosensitive pixel. The storage element is configured to store a first sensing result of the photosensitive pixel at a first time point. The displacement processing element is coupled to the storage element to receive the first sensing result. The displacement processing element is configured to generate displacement information, wherein an image frame with the displacement information is transmitted to the outside of the image sensor.

公开(公告)号：US20230261021A1

公开(公告)日：2023-08-17

申请号：US17750784

申请日：2022-05-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Jui Wang ,  Dun-Nian Yaung ,  Chen-Jong Wang ,  Ming-Chieh Hsu ,  Wei-Cheng Hsu ,  Yuichiro Yamashita

IPC分类号： H01L27/146 ,  H04N5/3745

CPC分类号： H01L27/1463 ,  H01L27/14614 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3745

摘要： Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.

公开(公告)号：US20230223412A1

公开(公告)日：2023-07-13

申请号：US17647931

申请日：2022-01-13

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Robert Michael GUIDASH ,  Muhammad Maksudur RAHMAN

IPC分类号： H01L27/146 ,  H04N5/3745 ,  H04N5/355 ,  H04N5/378

CPC分类号： H01L27/14612 ,  H04N5/37452 ,  H04N5/3559 ,  H01L27/14643 ,  H04N5/378

摘要： Transistor structures for a transistor may include a first source-drain region, a second source-drain region, and a channel region between the first and second source-drain regions overlapped by a gate structure. Transistor structures may be formed in a well of a first doping type. Isolation structures having the first doping type may be formed within the well. A lightly doped implant region of a second doping type for each of the source-drain regions may be formed within the well and separated from the isolation structures. A heavily doped surface implant region of the first doping type may extend across the surface of the well and cover the lightly doped implant region of each source-drain region. The surface implant region may be formed by patterning or by a blanket implantation process across the transistor structures.

公开(公告)号：US11683606B2

公开(公告)日：2023-06-20

申请号：US17284627

申请日：2019-10-16

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： Futa Mochizuki

IPC分类号： H04N5/374 ,  H04N5/3745 ,  H04N25/75 ,  H04N25/766 ,  H04N25/771 ,  H04N25/772

CPC分类号： H04N25/75 ,  H04N25/766 ,  H04N25/771 ,  H04N25/772

摘要： An imaging device of the present disclosure includes a plurality of pixels each including a light receiving element that performs photoelectric conversion on incident light to generate an electrical signal, the pixels outputs a detection signal when detecting that an amount of change of the electrical signal exceeds a predetermined threshold, and a control section that reads out, when pixels of a pixel combination of two or more pixels including a pixel of interest both output detection signals, the detection signals. Further, electronic equipment of the present disclosure includes the imaging device including the plurality of pixels and a detection section that have the above-mentioned configurations.

公开(公告)号：US20230179889A1

公开(公告)日：2023-06-08

申请号：US17540434

申请日：2021-12-02

申请人： OmniVision Technologies,Inc.

发明人： Chao-Fang Tsai ,  Zheng Yang ,  Chun-Hsiang Chang

IPC分类号： H04N5/3745 ,  H03M1/46 ,  H03M1/56 ,  H04N5/378

CPC分类号： H04N5/37455 ,  H03M1/468 ,  H03M1/462 ,  H03M1/56 ,  H04N5/378

摘要： A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.