公开(公告)号：US20070194391A1

公开(公告)日：2007-08-23

申请号：US11789338

申请日：2007-04-24

Applicant: Anand Murthy ,  Justin Brask ,  Andrew Westmeyer ,  Boyan Boyanov ,  Nick Lindert

Inventor： Anand Murthy ,  Justin Brask ,  Andrew Westmeyer ,  Boyan Boyanov ,  Nick Lindert

IPC: H01L29/76

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

公开(公告)号：US07202514B2

公开(公告)日：2007-04-10

申请号：US10418395

申请日：2003-04-17

Applicant: Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green ,  Anand Murthy

Inventor： Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green ,  Anand Murthy

IPC: H01L31/072

CPC classification number: H01L29/66287

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract translation: 本发明涉及一种形成双极结型晶体管（BJT）的方法，其包括在衬底上形成拓扑结构。 此后，在拓扑形成间隔物。 基底层由间隔物上方的外延硅和拓扑形成。 通过从间隔物的扩散形成在衬底中的泄漏块结构。 此后，BJT完成了基层和隔离层。

公开(公告)号：US20060151832A1

公开(公告)日：2006-07-13

申请号：US11233854

申请日：2005-09-09

Applicant: Anand Murthy ,  Robert Chau ,  Tahir Ghani

Inventor： Anand Murthy ,  Robert Chau ,  Tahir Ghani

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract translation: 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IATAT和/或DLIN 。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US20060148151A1

公开(公告)日：2006-07-06

申请号：US11029740

申请日：2005-01-04

Applicant: Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Jeffrey Wank

Inventor： Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Jeffrey Wank

IPC: H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7834

Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

公开(公告)号：US20060113634A1

公开(公告)日：2006-06-01

申请号：US11269477

申请日：2005-11-07

Applicant: Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

Inventor： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

IPC: H01L29/70

CPC classification number: H01L29/66287 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

公开(公告)号：US20050230760A1

公开(公告)日：2005-10-20

申请号：US11152266

申请日：2005-06-13

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

公开(公告)号：US06952040B2

公开(公告)日：2005-10-04

申请号：US09895697

申请日：2001-06-29

Applicant: Robert S. Chau ,  Jack Kavalieros ,  Anand Murthy ,  Brian Roberds ,  Brian S. Doyle

Inventor： Robert S. Chau ,  Jack Kavalieros ,  Anand Murthy ,  Brian Roberds ,  Brian S. Doyle

IPC: H01L21/3205 ,  H01L21/336 ,  H01L29/49 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/66772 ,  H01L29/41783 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78654 ,  Y10S977/70 ,  Y10S977/721 ,  Y10S977/936

Abstract: A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.

Abstract translation: 一种新颖的晶体管结构及其制造方法。 根据本发明，晶体管包括具有第一表面的本征硅体。 在本征硅体的第一表面上形成栅极电介质。 栅极电极形成在栅极电介质上，其中栅电极在栅极电介质上包括中间间隙功函数膜。 一对源极/漏极区域形成在本征硅体的相对侧上。

公开(公告)号：US20050184311A1

公开(公告)日：2005-08-25

申请号：US11107141

申请日：2005-04-14

Applicant: Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

Inventor： Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract translation: 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IATAT和/或DLIN 。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US06927140B2

公开(公告)日：2005-08-09

申请号：US10225586

申请日：2002-08-21

Applicant: Ravindra Soman ,  Anand Murthy

Inventor： Ravindra Soman ,  Anand Murthy

IPC: H01L21/205 ,  H01L21/331 ,  H01L29/10 ,  H01L21/8222

CPC classification number: H01L29/1004 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66242

Abstract: A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.

Abstract translation: 一种用于形成双极晶体管的基极的方法。 在反应室中使用硼掺杂气体的闪光形成窄碱以产生具有高硼浓度的窄碱。 该方法允许可靠地形成具有高硼浓度的碱，同时保持控制其它材料在衬底中沉积的可管理性。

公开(公告)号：US20050104160A1

公开(公告)日：2005-05-19

申请号：US10715971

申请日：2003-11-17

Applicant: Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

Inventor： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

IPC: H01L21/331 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66287 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

Abstract translation: 描述了双极晶体管及其制造。 通过在第一外延层上生长第二更重掺杂的外延层来形成非本征基区。 第二层在覆盖多晶硅发射器基座的下方延伸并与其绝缘。