公开(公告)号：US07005359B2

公开(公告)日：2006-02-28

申请号：US10715971

申请日：2003-11-17

Applicant: Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

Inventor： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

Abstract translation: 描述了双极晶体管及其制造。 通过在第一外延层上生长第二更重掺杂的外延层来形成非本征基区。 第二层在覆盖多晶硅发射器基座的下方延伸并与其绝缘。

公开(公告)号：US20050079660A1

公开(公告)日：2005-04-14

申请号：US10917165

申请日：2004-08-11

Applicant: Anand Murthy ,  Boyan Boyanov ,  Ravindra Soman ,  Robert Chau

Inventor： Anand Murthy ,  Boyan Boyanov ,  Ravindra Soman ,  Robert Chau

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66477 ,  H01L21/2254 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

Abstract translation: 晶体管通过生长锗源极和漏极区域，将掺杂杂质注入到锗中并随后对源极和漏极区域进行退火来制造，使得掺杂剂杂质扩散通过锗。 该方法比其中锗掺杂有p型或n型杂质的方法简单。 掺杂剂杂质易于通过锗扩散，但不容易通过下面的硅，使得锗和硅之间的界面充当扩散势垒，并确保掺杂剂原子在其中提高晶体管性能的区域中的位置。

公开(公告)号：US07517768B2

公开(公告)日：2009-04-14

申请号：US10404781

申请日：2003-03-31

Applicant: Ravindra Soman ,  Anand Murthy ,  Peter VanDerVoorn ,  Shahriar Ahmed

Inventor： Ravindra Soman ,  Anand Murthy ,  Peter VanDerVoorn ,  Shahriar Ahmed

IPC: H01L21/331

CPC classification number: H01L29/66242

Abstract: A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.

Abstract translation: 具有SiGe：C膜的双极晶体管和形成在SiGe：C薄膜下面的晶种层及其制造方法。 该方法包括将基板放置在反应器室中并将硅源气体引入反应器室以形成硅籽晶层。 反应室保持在低于45托的压力和约700℃至850℃之间的温度。形成种子层之后，停止硅源气体。 然后将反应器室同时调节至约70托和90托之间的压力以及约600℃和650℃之间的温度。引入硅源气体，锗源气体和碳源气体以形成 种子层上的SiGe：C膜。

公开(公告)号：US20060113634A1

公开(公告)日：2006-06-01

申请号：US11269477

申请日：2005-11-07

Applicant: Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

Inventor： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

IPC: H01L29/70

CPC classification number: H01L29/66287 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

公开(公告)号：US06927140B2

公开(公告)日：2005-08-09

申请号：US10225586

申请日：2002-08-21

Applicant: Ravindra Soman ,  Anand Murthy

Inventor： Ravindra Soman ,  Anand Murthy

IPC: H01L21/205 ,  H01L21/331 ,  H01L29/10 ,  H01L21/8222

CPC classification number: H01L29/1004 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66242

Abstract: A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.

Abstract translation: 一种用于形成双极晶体管的基极的方法。 在反应室中使用硼掺杂气体的闪光形成窄碱以产生具有高硼浓度的窄碱。 该方法允许可靠地形成具有高硼浓度的碱，同时保持控制其它材料在衬底中沉积的可管理性。

公开(公告)号：US20050104160A1

公开(公告)日：2005-05-19

申请号：US10715971

申请日：2003-11-17

Applicant: Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

Inventor： Shahriar Ahmed ,  Ravindra Soman ,  Anand Murthy ,  Mark Bohr

IPC: H01L21/331 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66287 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

Abstract translation: 描述了双极晶体管及其制造。 通过在第一外延层上生长第二更重掺杂的外延层来形成非本征基区。 第二层在覆盖多晶硅发射器基座的下方延伸并与其绝缘。

公开(公告)号：US06723622B2

公开(公告)日：2004-04-20

申请号：US10081099

申请日：2002-02-21

Applicant: Anand Murthy ,  Ravindra Soman ,  Boyan Boyanov

Inventor： Anand Murthy ,  Ravindra Soman ,  Boyan Boyanov

IPC: H01L21365

CPC classification number: C30B25/02 ,  C30B29/08 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66916 ,  Y10T428/12674

Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.

Abstract translation: 用于半导体器件的锗膜的复合材料及其制造方法。 该方法包括在沉积室中在半导体衬底上生长渐变锗膜，同时降低沉积温度并减少硅源气体并增加锗源气体超过预定时间量。 分级锗膜包括超薄硅 - 锗缓冲层和锗膜。

公开(公告)号：US20210202378A1

公开(公告)日：2021-07-01

申请号：US16728887

申请日：2019-12-27

Applicant: Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/762 ,  H01L21/768

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US20130153965A1

公开(公告)日：2013-06-20

申请号：US13764675

申请日：2013-02-11

Applicant: Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

Inventor： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

IPC: H01L29/78

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract translation: 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

公开(公告)号：US08373154B2

公开(公告)日：2013-02-12

申请号：US12609711

申请日：2009-10-30

Applicant: Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

Inventor： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

IPC: H01L29/08 ,  H01L31/0312 ,  H01L29/12 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.