公开(公告)号：US20080169514A1

公开(公告)日：2008-07-17

申请号：US11652895

申请日：2007-01-11

Applicant: Fu-Lung Hsueh ,  Sung-Chieh Lin

Inventor： Fu-Lung Hsueh ,  Sung-Chieh Lin

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the first set of contacts and the second set of plugs are coupled together as a first resistor segment to provide a predetermined resistance for the integrated circuit.

Abstract translation: 用于集成电路的电阻器结构包括连接在半导体层和第一导电层之间的第一组触点; 以及连接在所述第一导电层和第二导电层之间的第二组插头，其中所述第一组触点和所述第二组插头作为第一电阻器段耦合在一起以为所述集成电路提供预定电阻。

公开(公告)号：US07382661B1

公开(公告)日：2008-06-03

申请号：US11672406

申请日：2007-02-07

Applicant: Yang-Chieh Lin

Inventor： Yang-Chieh Lin

IPC: G11C16/00

CPC classification number: G11C16/10

Abstract: A program method for a flash memory semiconductor device includes the steps of providing a bit line voltage for programming a group of memory cells and detecting if the bit line voltage meets a selected target voltage. When the bit line voltage meets the selected target voltage, a program operation is performed on the group of memory cells. When the bit line voltage does not meet the selected target voltage, the programming operation is individually performed on at least a first subgroup of memory cells from the group and a second subgroup of memory cells from the group.

Abstract translation: 一种用于闪速存储器半导体器件的程序方法，包括以下步骤：提供用于对一组存储器单元进行编程的位线电压，以及检测位线电压是否满足所选择的目标电压。 当位线电压满足所选择的目标电压时，对存储器单元组执行编程操作。 当位线电压不满足所选择的目标电压时，对组中的至少第一组存储器单元和来自组的存储器单元的第二子组分别进行编程操作。

公开(公告)号：US07381604B2

公开(公告)日：2008-06-03

申请号：US11423457

申请日：2006-06-12

Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

IPC: H01L21/336

CPC classification number: H01L21/823425 ,  H01L21/76224 ,  H01L21/823412 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7848

Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region. A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 通道区域设置在衬底中，并且栅堆叠设置在应变通道区域上。 一对源极/漏极区域相邻地设置在衬底中，与沟道区域相邻，其中源极/漏极区域中的每个源极/漏极区域包括具有第二自然晶格常数而不是第一自然晶格的第二半导体材料的晶格失配区域 常数，对应于栅极叠层的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

公开(公告)号：US07375759B2

公开(公告)日：2008-05-20

申请号：US10707949

申请日：2004-01-27

Applicant: Yu-Chieh Lin

Inventor： Yu-Chieh Lin

IPC: H04N5/225 ,  G03B15/03 ,  G03B15/06 ,  H04N9/04

CPC classification number: H04N5/2259 ,  H04N5/2254

Abstract: A digital image capturing apparatus includes a housing, a first hole installed on the front side of the housing for inputting light from the front, a second hole installed on the rear side of the housing for inputting light from the rear, a reflector module installed in the housing for reflecting the light input from the first hole or the second hole, a photosensor installed in the housing for sensing the light from the reflector module, and an image generating module installed in the housing for generating an image according to the light sensed by the photosensor.

Abstract translation: 一种数字图像拍摄装置，包括壳体，安装在壳体前侧的用于从前面输入光的第一孔，安装在壳体后侧的用于从后面输入光的第二孔，安装在 用于反射从第一孔或第二孔输入的光的壳体，安装在壳体中用于感测来自反射器模块的光的光电传感器，以及安装在壳体中的图像产生模块，用于根据由 光电传感器。

公开(公告)号：US07357838B2

公开(公告)日：2008-04-15

申请号：US11074738

申请日：2005-03-08

Applicant: Chun Chieh Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

Inventor： Chun Chieh Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

IPC: C30B23/00

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

Abstract: A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.

Abstract translation: 提供了在松弛的低缺陷密度半导体合金层（例如SiGe）上形成应变硅层的方法。

公开(公告)号：US20070244686A1

公开(公告)日：2007-10-18

申请号：US11481846

申请日：2006-07-07

Applicant: Yaong-Jar Chang ,  Yung-Chieh Lin ,  Jung-Chi Ho ,  Pei-Wen Luo

Inventor： Yaong-Jar Chang ,  Yung-Chieh Lin ,  Jung-Chi Ho ,  Pei-Wen Luo

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A calibration method of a mixed mode simulation calibrates standard delay times in a standard delay format and includes obtaining a digital output circuit from a digital circuit, obtaining an analog output circuit from an analog circuit, performing a simulation on the digital output circuit connected to the analog output circuit to obtain an ideal output, obtaining a first delay time according to the standard delay times of the digital output circuit, performing a calibrative analog-to-digital mixed mode simulation using the first delay time to obtain an analog-to-digital mixed output, comparing the ideal output and the analog-to-digital mixed output to calibrate the first delay time, and calibrating the standard delay times of the digital output circuit according to the calibrated first delay time.

Abstract translation: 混合模式模拟的校准方法以标准延迟格式校准标准延迟时间，并且包括从数字电路获得数字输出电路，从模拟电路获得模拟输出电路，对连接到模拟电路的数字输出电路执行仿真 模拟输出电路以获得理想输出，根据数字输出电路的标准延迟时间获得第一延迟时间，使用第一延迟时间执行校准模数混合模式仿真，以获得模数转换 混合输出，比较理想输出和模数混合输出以校准第一延迟时间，并根据校准的第一延迟时间校准数字输出电路的标准延迟时间。

公开(公告)号：US20070174502A1

公开(公告)日：2007-07-26

申请号：US11307072

申请日：2006-01-23

Applicant: Cheng-Chieh Lin ,  Jih-Liang Juang ,  Ying-Chu Chen

Inventor： Cheng-Chieh Lin ,  Jih-Liang Juang ,  Ying-Chu Chen

IPC: G06F3/00

CPC classification number: G06F13/1694

Abstract: A method for detecting a type of a non-volatile memory. The method includes issuing one of a sequence of reading identification commands to detect the type of the non-volatile memory; obtaining a response data from the non-volatile memory; judging whether the response data matches any type of a plurality of types of non-volatile memory; utilizing another reading identification command of the sequence of reading identification commands to detect the type of the non-volatile memory when the response data does not match any type of the plurality of types of non-volatile memory; and determining the type of the non-volatile memory according to the response data when the response data match one type of the plurality of types of non-volatile memory.

Abstract translation: 一种用于检测非易失性存储器的类型的方法。 该方法包括发出读取识别命令的序列之一以检测非易失性存储器的类型; 从非易失性存储器获得响应数据; 判断响应数据是否匹配任何类型的多种类型的非易失性存储器; 当所述响应数据与所述多种类型的所述非易失性存储器不匹配时，利用所述读取识别命令序列的另一读取识别命令来检测所述非易失性存储器的类型; 以及当所述响应数据与所述多种类型的所述非易失性存储器匹配时，根据所述响应数据确定所述非易失性存储器的类型。

公开(公告)号：US20070164439A1

公开(公告)日：2007-07-19

申请号：US11334849

申请日：2006-01-19

Applicant: Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

Inventor： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC: H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

Abstract translation: 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

公开(公告)号：US07235838B2

公开(公告)日：2007-06-26

申请号：US10881372

申请日：2004-06-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee

IPC: H01L27/108

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

公开(公告)号：US20070127275A1

公开(公告)日：2007-06-07

申请号：US11607977

申请日：2006-12-04

Applicant: Yuan-Cheng Chuang ,  Chun-Teh Chen ,  Ying-Chieh Lin ,  Jenn-Jong Shieh

Inventor： Yuan-Cheng Chuang ,  Chun-Teh Chen ,  Ying-Chieh Lin ,  Jenn-Jong Shieh

IPC: H02M1/12

CPC classification number: H02M3/335 ,  Y10T307/544

Abstract: The invention discloses a switching power supply capable of reducing a low-frequency secondary-side common-mode voltage. The power supply mainly has two common-mode filtering circuit devices to prevent an AC voltage and an AC current from coupling to a secondary side of a transformer. Thus, the electrical safety and the quality in use of the associated electronic apparatus can be enhanced, a potential difference between the electronic apparatus and the ground may be greatly reduced, and an AC hum of a speaker coupled to an output of the power supply may be reduced or even eliminated.

Abstract translation: 本发明公开了一种能够降低低频二次侧共模电压的开关电源。 电源主要具有两个共模滤波电路装置，以防止交流电压和交流电流耦合到变压器的次级侧。 因此，可以增强电子安全性和相关联的电子设备的使用质量，电子设备和地面之间的电位差可以大大降低，并且耦合到电源的输出端的扬声器的AC嗡嗡声可以 减少甚至消除。