Scanning control device for a capacitive touch panel
    91.
    发明申请
    Scanning control device for a capacitive touch panel 审中-公开
    用于电容式触摸屏的扫描控制装置

    公开(公告)号:US20070291012A1

    公开(公告)日:2007-12-20

    申请号:US11519094

    申请日:2006-09-12

    Applicant: Chin-Fu Chang

    Inventor: Chin-Fu Chang

    CPC classification number: G06F3/044

    Abstract: A scanning control device for a capacitive touch panel uses voltage driving/current detecting circuits to connect to a top conductive layer of the touch panel. Output terminals of all voltage driving/current detecting units are connected to a signal processing unit through a switching unit. Output data of the signal processing unit are output to a central control unit. If the touch panel is pressed, all voltage driving/current detecting circuits detect current values at four corners of the top conductive layer and sequentially output the current values to the signal processing unit. The processed data output from the signal processing unit are transmitted to the central control unit. Based on the received data, the central control unit calculates coordinate of a pressed point on the touch panel.

    Abstract translation: 用于电容式触摸面板的扫描控制装置使用电压驱动/电流检测电路连接到触摸面板的顶部导电层。 所有电压驱动/电流检测单元的输出端子通过开关单元连接到信号处理单元。 信号处理单元的输出数据被输出到中央控制单元。 如果按下触摸面板,则所有电压驱动/电流检测电路检测顶部导电层的四个角处的电流值,并将电流值依次输出到信号处理单元。 从信号处理单元输出的处理后的数据被发送到中央控制单元。 基于所接收的数据,中央控制单元计算触摸面板上的按压点的坐标。

    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    92.
    发明授权
    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 失效
    单片,组合非易失性存储器允许字节,页和块写入,无扰动和分割,在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号:US07283401B2

    公开(公告)日:2007-10-16

    申请号:US11391507

    申请日:2006-03-28

    Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    Abstract translation: 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极,以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上,浮动栅极与源极区域和漏极区域的边缘对准,并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50%的相对小的耦合比,以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程,并以相对高的电压用Fowler Nordheim隧道擦除。

    Image description system and method
    93.
    发明授权
    Image description system and method 有权
    图像描述系统和方法

    公开(公告)号:US07254285B1

    公开(公告)日:2007-08-07

    申请号:US09831215

    申请日:1999-11-05

    CPC classification number: G06K9/4685

    Abstract: Systems and methods for describing image content establish image description records which include an object set (24), an object hierarchy (26) and entity relation graphs (28). For image content, image objects can include global objects (O0 8) and local objects (O1 2 and O2 6). The image objects are further defined by a number of features of different classes (36, 38 and 40), which in turn are further defined by a number of feature descriptors. The relationships between and among the objects in the object set are defined by the object hierarchy (26) and entity relation graphs (28). The image description records provide a standard vehicle for describing the content and context of image information for subsequent access and processing by computer applications such as search engines, filters, and archive systems.

    Abstract translation: 用于描述图像内容的系统和方法建立包括对象集(24),对象层次(26)和实体关系图(28)的图像描述记录。 对于图像内容,图像对象可以包括全局对象(O 0 8)和本地对象(O 1 2和O 2 6)。 图像对象由不同类别(36,38和40)的许多特征进一步限定,这些特征又由许多特征描述符进一步限定。 对象集合中的对象之间和之间的关系由对象层次结构(26)和实体关系图(28)定义。 图像描述记录提供用于描述图像信息的内容和上下文的标准车辆,用于随后由计算机应用(例如搜索引擎,过滤器和归档系统)的访问和处理。

    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
    94.
    发明申请
    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
    组合非易失性存储器采用统一技术与字节,页面和块写入以及同步读写操作

    公开(公告)号:US20070133341A1

    公开(公告)日:2007-06-14

    申请号:US11633334

    申请日:2006-12-04

    Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

    Abstract translation: 描述了组合EEPROM和闪存,其中包含单元,其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。 使选择晶体管足够小,以便允许EEPROM单元适应闪存单元的位线间距,这有助于将两个存储器组合成包含两个单元的存储体。 闪存单元被块擦除时,EEPROM单元被字节擦除。 小选择晶体管具有小的沟道长度和宽度,其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

    Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    95.
    发明申请
    Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 失效
    新颖的单片,组合非易失性存储器允许字节,页和块写入,在单元阵列中没有干扰和分割,使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号:US20070047302A1

    公开(公告)日:2007-03-01

    申请号:US11391507

    申请日:2006-03-28

    Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    Abstract translation: 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极,以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上,浮动栅极与源极区域和漏极区域的边缘对准,并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50%的相对小的耦合比,以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程,并以相对高的电压用Fowler Nordheim隧道擦除。

    Low temperature method for metal deposition
    96.
    发明授权
    Low temperature method for metal deposition 有权
    金属沉积低温法

    公开(公告)号:US07176081B2

    公开(公告)日:2007-02-13

    申请号:US10851044

    申请日:2004-05-20

    CPC classification number: H01L21/2855 H01L21/32051 H01L28/60

    Abstract: A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.

    Abstract translation: 公开了一种适用于在金属 - 绝缘体 - 金属(MIM)电容器的制造中在基底上沉积金属膜的新颖的低温金属沉积方法。 该方法包括使用小于一般约270℃的沉积温度在基板上沉积金属膜。所得到的金属膜的特征在于增强的厚度均匀性和减小的晶粒聚集,否则倾向于降低电容器或其它的操作完整性 金属膜是其一部分的装置。 此外,金属膜的特征在于本征击穿电压(V BAT)改善。

    Handle structure for ball striking equipments
    97.
    发明申请
    Handle structure for ball striking equipments 失效
    打击设备的手柄结构

    公开(公告)号:US20070032309A1

    公开(公告)日:2007-02-08

    申请号:US11195471

    申请日:2005-08-02

    Applicant: Chun-Fu Chang

    Inventor: Chun-Fu Chang

    Abstract: A handle structure for ball striking equipments includes an underlisting for passing a handle rod of a ball striking equipment through its interior and having a first section and a second section at its exterior, a wrapping strap fixed on the outside of the second section, and the wrapping strap and the first section of the underlisting divide a handle holding section into two gripping sections, and the first section gives a shock absorbing and a slippery resisting effects, and the wrapping strap provides a soft, comfortable and slippery-proof gripping effect.

    Abstract translation: 用于击球设备的把手结构包括:用于使球打击设备的手柄杆穿过其内部并且在其外部具有第一部分和第二部分的下部突出物,固定在第二部分的外侧的包裹带, 包装带,下部的第一部分将手柄保持部分分成两个抓握部分,第一部分给予冲击吸收和防滑效果,并且包裹带提供柔软,舒适和防滑的夹持效果。

    Shock isolation structure applied in optical disc drive

    公开(公告)号:US20060294533A1

    公开(公告)日:2006-12-28

    申请号:US11157831

    申请日:2005-06-22

    CPC classification number: G11B33/08

    Abstract: A shock isolation structure applied in an optical disc drive is provided. The shock isolation structure includes a bottom portion, a top portion, and a neck portion jointing the bottom portion and the top portion. The portions have a through hole running through the top surface of the top portion and the bottom surface of the bottom portion along a run-through central line. In the neck portion, any ring-shaped cross section using the run-through central line as the normal has a first wall thickness on a first extension line starting from the run-through central line and extending towards the outer peripheral of the ring-shaped cross section, and has a second wall thickness on a second extension line starting from the run-through central line and extending towards the outer peripheral of the ring-shaped cross section. The first wall thickness is larger than the second wall thickness.

    Direct current offset canceling circuit of trans-impedance amplifier and automatic gain control trans-impedance amplifier thereof
    99.
    发明申请
    Direct current offset canceling circuit of trans-impedance amplifier and automatic gain control trans-impedance amplifier thereof 有权
    跨阻放大器的直流偏移消除电路及其自动增益控制跨阻放大器

    公开(公告)号:US20060290432A1

    公开(公告)日:2006-12-28

    申请号:US11232860

    申请日:2005-09-23

    CPC classification number: H03F3/45973

    Abstract: A direct current (DC) offset canceling circuit of a trans-impedance amplifier and an automatic gain control trans-impedance amplifier is provided, including: a trans-impedance amplifier for receiving an input current and converting the input current into a first voltage signal, while the trans-impedance amplifier is provided with a plurality of inverters connected in series, wherein a sample node is defined between each inverter; a DC detector for retrieving and comparing the signals at any sample node, thereby generating a trigger signal according to the comparison; a DC eliminator for providing a path to the DC component of the input current in response to the triggering by the signal trigger, to eliminate the DC component; a reference voltage unit for outputting a reference voltage value; and a voltage output amplifier for comparing the reference voltage and the first voltage signal, to amplify the output of a second voltage signal.

    Abstract translation: 提供了一种跨阻放大器和自动增益控制跨阻放大器的直流(DC)偏移消除电路,包括:用于接收输入电流并将输入电流转换为第一电压信号的跨阻放大器, 而跨阻放大器设置有串联连接的多个反相器,其中在每个反相器之间限定采样节点; DC检测器,用于检索和比较任何采样节点处的信号,从而根据比较产生触发信号; DC消除器,用于响应于信号触发的触发而提供到输入电流的DC分量的路径,以消除DC分量; 用于输出参考电压值的参考电压单元; 以及用于比较参考电压和第一电压信号的电压输出放大器,以放大第二电压信号的输出。

    Method and system for preliminary data processing before printing

    公开(公告)号:US20060227369A1

    公开(公告)日:2006-10-12

    申请号:US11099634

    申请日:2005-04-06

    Applicant: Fu-Chang Lin

    Inventor: Fu-Chang Lin

    Abstract: A method and system for preliminary data processing before printing is disclosed. The steps executed by said system comprises: dividing a page into a plurality of bands including a Mth band and a (M+1)th band; converting a color format of the Mth band; transferring the Mth band to a printer for storing, and converting the color format of the (M+1)th band in the period of transferring the Mth band; and printing the Mth band, wherein the printing does not start until the printer receives 50%-100% bands. During the printing, the color format of the residual bands continues to convert and the converted residual bands continue to transfer to the printer until the page is finished printing.

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