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158 条记录 (耗时 0.022 秒)

    Method of fabricating contact pads of a semiconductor device
    92.
    发明授权
    Method of fabricating contact pads of a semiconductor device 有权
    制造半导体器件的接触焊盘的方法

    公开(公告)号：US06458680B2

    公开(公告)日：2002-10-01

    申请号：US09371835

    申请日：1999-08-11

    申请人： Tae-Young Chung ,  Jae-Goo Lee ,  Gwan-Hyeob Koh

    发明人： Tae-Young Chung ,  Jae-Goo Lee ,  Gwan-Hyeob Koh

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/76895

    摘要： An upper insulating layer is formed on a semiconductor substrate, the upper insulating layer having an etch selection ratio relative to a lower insulating layer. The upper insulating layer is anisotropically etched by using a contact pad forming mask, to form an opening exposing an upper surface of the semiconductor substrate between conductive patterns on the substrate. The side walls of the upper insulating layer are then isotropically etched, using the above mask again, to expand the size of the opening. The expanded opening is then filled with a conductive layer to form a contact pad to be electrically connected to the semiconductor substrate.

    摘要翻译： 在半导体衬底上形成上绝缘层，上绝缘层相对于下绝缘层具有蚀刻选择比。 通过使用接触焊盘形成掩模对上绝缘层进行各向异性蚀刻，以形成在衬底上的导电图案之间暴露半导体衬底的上表面的开口。 然后再次使用上述掩模对上绝缘层的侧壁进行各向同性蚀刻，以扩大开口的尺寸。 然后用导电层填充扩大的开口以形成电连接到半导体衬底的接触焊盘。

    Semiconductor memory device using double layered capping pattern and semiconductor memory device formed thereby
    93.
    发明授权
    Semiconductor memory device using double layered capping pattern and semiconductor memory device formed thereby 有权
    使用双层封盖图案的半导体存储器件和由此形成的半导体存储器件

    公开(公告)号：US06403996B1

    公开(公告)日：2002-06-11

    申请号：US09777756

    申请日：2001-02-05

    申请人： Jae-Goo Lee

    发明人： Jae-Goo Lee

    IPC分类号： H01L27108

    CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894

    摘要： A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconnection patterns includes a interconnection line and a double layered capping pattern. The double layered capping pattern includes a first capping pattern and a second capping pattern, which are sequentially stacked. The second capping pattern is formed of a material layer having an etching selectivity with respect to the first capping pattern. A planarized separating layer is formed between the adjacent interconnection patterns. The substrate having the planarized separating layer is covered with a sacrificial layer. The sacrificial layer is formed of a material layer having a wet etching selectivity with respect to the planarized separating layer. The sacrificial layer and the planarized separating layer are patterned to form a hole exposing a predetermined region of the semiconductor substrate. The hole is filled with a conductive pattern. The sacrificial layer is then removed to thereby protrude the conductive pattern. The conductive pattern and the second capping pattern are planarized, thereby forming a conductive plug in the hole and concurrently exposing the first capping pattern.

    摘要翻译： 提供一种使用双层封盖图案形成半导体存储器件的方法和由此形成的半导体存储器件。 多个互连图案形成在半导体衬底上。 每个互连图案包括互连线和双层封盖图案。 双层封盖图案包括顺序堆叠的第一封盖图案和第二封盖图案。 第二封盖图案由相对于第一封盖图案具有蚀刻选择性的材料层形成。 在相邻的互连图案之间形成平坦化的分离层。 具有平坦化分离层的基板被牺牲层覆盖。 牺牲层由相对于平坦化分离层具有湿蚀刻选择性的材料层形成。 将牺牲层和平坦化分离层图案化以形成暴露半导体衬底的预定区域的孔。 该孔填充有导电图案。 然后去除牺牲层，从而突出导电图案。 导电图案和第二封盖图案被平坦化，从而在孔中形成导电插塞并同时暴露第一封盖图案。

    Method of forming self-aligned contact pads on electrically conductive lines
    94.
    发明授权
    Method of forming self-aligned contact pads on electrically conductive lines 有权
    在导电线上形成自对准接触焊盘的方法

    公开(公告)号：US06268252B1

    公开(公告)日：2001-07-31

    申请号：US09442523

    申请日：1999-11-18

    申请人： Jae-Goo Lee ,  Chang-Hyun Cho

    发明人： Jae-Goo Lee ,  Chang-Hyun Cho

    IPC分类号： H01L21336

    CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76895 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/00

    摘要： Self aligned contact pads in a semiconductor device and a method for forming thereof wherein etching back process is carried out on the contact pad comprising material and insulating layer down to the top surface of a capping layer of a gate electrode, and also portions of the capping layer is selectively etched with respect to the contact pad composing material at the end of the etching back process and thereby forming the contact pads to be electrically separated from each other. SAC is opened by etching insulating layer selectively to the capping layer using SAC gate mask. A conductive material as for SAC pad is deposited over the insulating layer to fill the SAC opening. Etching back process is carried out to form the SAC pad.

    摘要翻译： 半导体器件中的自对准接触焊盘及其形成方法，其中在包括材料和绝缘层的接触焊盘上进行蚀刻回加工，直到栅电极的覆盖层的顶表面，以及封盖的部分 在蚀刻返回处理结束时相对于接触焊盘构成材料选择性地蚀刻层，从而形成彼此电分离的接触焊盘。 使用SAC栅极掩模，通过将绝缘层选择性地蚀刻到覆盖层来打开SAC。 用于SAC焊盘的导电材料沉积在绝缘层上以填充SAC开口。 进行蚀刻处理以形成SAC焊盘。

    Method of fabricating memory device
    95.
    发明授权
    Method of fabricating memory device 有权

    公开(公告)号：US09748261B2

    公开(公告)日：2017-08-29

    申请号：US14832285

    申请日：2015-08-21

    申请人： Jae-goo Lee ,  Young-woo Park

    发明人： Jae-goo Lee ,  Young-woo Park

    IPC分类号： H01L21/336 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11575

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11575

    摘要： A method of fabricating a memory device includes alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, forming a channel hole by etching the insulating layers and the sacrificial layers to expose a partial region of the substrate, forming a channel structure in the channel hole, forming an opening by etching the insulating layers and the sacrificial layers to exposed a portion of the substrate, forming a plurality of side openings that include first side openings and a second side opening by removing the sacrificial layers through the opening, forming gate electrodes to fill the first side openings, and forming a blocking layer to fill the second side opening.

    NON-VOLATILE MEMORY DEVICE
    97.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20170092651A1

    公开(公告)日：2017-03-30

    申请号：US15264902

    申请日：2016-09-14

    申请人： Jong-Won KIM ,  Chang-Seok KANG ,  Young-Woo PARK ,  Jae-Goo LEE ,  Jae-Duk LEE

    发明人： Jong-Won KIM ,  Chang-Seok KANG ,  Young-Woo PARK ,  Jae-Goo LEE ,  Jae-Duk LEE

    IPC分类号： H01L27/115

    CPC分类号： H01L27/1157 ,  H01L27/11582

    摘要： A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

    SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL AND AIR GAP, AND METHOD OF MANUFACTURING THEREOF
    98.
    发明申请
    SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL AND AIR GAP, AND METHOD OF MANUFACTURING THEREOF 有权
    具有垂直通道和空气隙的半导体器件及其制造方法

    公开(公告)号：US20150380431A1

    公开(公告)日：2015-12-31

    申请号：US14642086

    申请日：2015-03-09

    申请人： KOHJI KANAMORI ,  CHUNG-JIN KIM ,  YOUNG-WOO PARK ,  JAE-GOO LEE ,  JAE-DUK LEE ,  MOO-RYM CHOI

    发明人： KOHJI KANAMORI ,  CHUNG-JIN KIM ,  YOUNG-WOO PARK ,  JAE-GOO LEE ,  JAE-DUK LEE ,  MOO-RYM CHOI

    IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

    摘要： A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.

    摘要翻译： 提供半导体器件。 字线形成在基板上。 在两个相邻字线之间插入气隙。 通道结构穿过字线和气隙。 存储单元插入在每个字线和通道结构之间。 存储单元包括阻挡图案，电荷陷阱图案和隧道绝缘图案。 阻挡图案保形地覆盖每个字线的顶表面，底表面和第一侧表面。 第一侧表面与通道结构相邻。 电荷陷阱图案仅插入在第一侧表面和沟道结构之间。

    Three dimensional semiconductor memory devices and methods of fabricating the same
    99.
    发明授权
    Three dimensional semiconductor memory devices and methods of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08952443B2

    公开(公告)日：2015-02-10

    申请号：US13222173

    申请日：2011-08-31

    申请人： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

    发明人： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L21/28

    CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

    摘要： A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

    摘要翻译： 一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。 每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。 而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。

    VERTICAL SEMICONDUCTOR DEVICE
    100.
    发明申请
    VERTICAL SEMICONDUCTOR DEVICE 有权
    垂直半导体器件

    公开(公告)号：US20150008499A1

    公开(公告)日：2015-01-08

    申请号：US14267909

    申请日：2014-05-02

    申请人： Jae-goo Lee ,  Young-woo Park ,  Jin-taek Park

    发明人： Jae-goo Lee ,  Young-woo Park ,  Jin-taek Park

    IPC分类号： H01L29/78 ,  H01L29/792 ,  H01L29/788

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L27/11273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/785 ,  H01L29/7889 ,  H01L29/7926

    摘要： A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

    摘要翻译： 垂直半导体器件包括从垂直于衬底的上表面的第一方向上从衬底延伸的沟道结构，以及顺序地形成在沟道结构的侧表面上的接地选择线，字线和串选择线 第一个要相互分离的方向。 通道结构包括形成在通道结构的侧壁部分之间的突出区域，其在接地选择线和衬底的上表面之间，突出区域在与第一方向垂直的水平方向上突出。