公开(公告)号：US07180118B2

公开(公告)日：2007-02-20

申请号：US10830895

申请日：2004-04-22

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

公开(公告)号：US06355547B1

公开(公告)日：2002-03-12

申请号：US09645968

申请日：2000-08-24

申请人： Jae-Goo Lee ,  Chang-Hyun Cho ,  Gwan-Hyeob Koh

发明人： Jae-Goo Lee ,  Chang-Hyun Cho ,  Gwan-Hyeob Koh

IPC分类号： H01L23209

CPC分类号： H01L27/10873 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

摘要： A method of manufacturing a self-aligned contact pad for the fabrication of an integrated circuit is disclosed. A plurality of gate structures is formed on the substrate. A first insulating layer is formed over the plurality of gate structures. Then, a second insulating layer is formed over the first insulating layer and filling spaces between the gate structures. Next, a portion of second insulating layer is removed between the gate structures, thereby forming a plurality of contact holes between the gate structures and exposing a portion of the first insulating layer. The exposed portion of the first insulating layer is etched away to form a gate spacer on the sidewalls of the gate structures and exposing surfaces of active regions of the substrate. Finally, the plurality of contact holes are filled with a first conductive layer and the first conductive layer is planarized to form contact pads.

摘要翻译： 公开了一种用于制造集成电路的自对准接触焊盘的制造方法。 在基板上形成多个栅极结构。 在多个栅极结构上形成第一绝缘层。 然后，在第一绝缘层上形成第二绝缘层，并在栅极结构之间填充空间。 接下来，在栅极结构之间移除第二绝缘层的一部分，从而在栅极结构之间形成多个接触孔，并露出第一绝缘层的一部分。 蚀刻掉第一绝缘层的暴露部分，以在栅极结构的侧壁和衬底的有源区域的暴露表面上形成栅极间隔物。 最后，多个接触孔填充有第一导电层，并且第一导电层被平坦化以形成接触焊盘。

公开(公告)号：US06337275B1

公开(公告)日：2002-01-08

申请号：US09334669

申请日：1999-06-17

申请人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

发明人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/76834

摘要： A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping layer disposed thereon, an insulating layer for gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. SAC then are opened in the interlayer insulating layer while concurrently forming single-layer gate spacers.

摘要翻译： 半导体器件中的自对准接触（SAC）焊盘及其形成方法，其中SAC开口与单层栅极间隔物同时形成。 在形成具有设置在其上的栅电极和覆盖层的堆叠栅极图案之后，在其上沉积栅极间隔物的绝缘层。 然后在绝缘层上沉积层间绝缘层。 层间绝缘层相对于覆盖层和绝缘层具有蚀刻选择性。 然后在层间绝缘层中打开SAC，同时形成单层栅极间隔物。

公开(公告)号：US06268252B1

公开(公告)日：2001-07-31

申请号：US09442523

申请日：1999-11-18

申请人： Jae-Goo Lee ,  Chang-Hyun Cho

发明人： Jae-Goo Lee ,  Chang-Hyun Cho

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76895 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/00

摘要： Self aligned contact pads in a semiconductor device and a method for forming thereof wherein etching back process is carried out on the contact pad comprising material and insulating layer down to the top surface of a capping layer of a gate electrode, and also portions of the capping layer is selectively etched with respect to the contact pad composing material at the end of the etching back process and thereby forming the contact pads to be electrically separated from each other. SAC is opened by etching insulating layer selectively to the capping layer using SAC gate mask. A conductive material as for SAC pad is deposited over the insulating layer to fill the SAC opening. Etching back process is carried out to form the SAC pad.

摘要翻译： 半导体器件中的自对准接触焊盘及其形成方法，其中在包括材料和绝缘层的接触焊盘上进行蚀刻回加工，直到栅电极的覆盖层的顶表面，以及封盖的部分 在蚀刻返回处理结束时相对于接触焊盘构成材料选择性地蚀刻层，从而形成彼此电分离的接触焊盘。 使用SAC栅极掩模，通过将绝缘层选择性地蚀刻到覆盖层来打开SAC。 用于SAC焊盘的导电材料沉积在绝缘层上以填充SAC开口。 进行蚀刻处理以形成SAC焊盘。

公开(公告)号：US07476585B2

公开(公告)日：2009-01-13

申请号：US11621507

申请日：2007-01-09

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

IPC分类号： H01L21/8239

CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

公开(公告)号：US06465310B2

公开(公告)日：2002-10-15

申请号：US09892125

申请日：2001-06-26

申请人： Jae-Goo Lee ,  Chang-Hyun Cho

发明人： Jae-Goo Lee ,  Chang-Hyun Cho

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76895 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/00

摘要： Self aligned contact pads in a semicondductor device and a method for forming thereof within etching back process is carried out on the contact pad comprising material and insulating layer down to the top surface of a capping layer of a gate electrode, and also portions of the capping layer is selectively etched with respect to the contact pad composing material at the end of the etching back process and thereby forming the contact pads to be electrically separated from each other. SAC is opened by etching insulating layer selectively to the capping layer using SAC gate mask. A conductive material as for SAC pad is deposited over the insulating layer to fill the SAC opening. Etching back process is carried out to form the SAC pad.

摘要翻译： 在半导体器件中的自对准接触焊盘及其在回蚀工艺中形成的方法在包括材料和绝缘层的接触焊盘上进行到栅电极的覆盖层的顶表面，还有部分封盖 在蚀刻返回处理结束时相对于接触焊盘构成材料选择性地蚀刻层，从而形成彼此电分离的接触焊盘。 使用SAC栅极掩模，通过将绝缘层选择性地蚀刻到覆盖层来打开SAC。 用于SAC焊盘的导电材料沉积在绝缘层上以填充SAC开口。 进行蚀刻处理以形成SAC焊盘。

公开(公告)号：US06204161B1

公开(公告)日：2001-03-20

申请号：US09418595

申请日：1999-10-15

申请人： Tae-Young Chung ,  Jae-Goo Lee ,  Chang-Hyun Cho

发明人： Tae-Young Chung ,  Jae-Goo Lee ,  Chang-Hyun Cho

IPC分类号： H01L21336

CPC分类号： H01L27/10855 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned contact pads in a semiconductor device and a method for forming the same are provided. These self-aligned contact pads can increase the upper surface of the contact pads to increase alignment margins. Portions of the gate mask are undercut, increasing the spaces between the gate structures. As a result, contact pads that are filled in these spaces have an increased upper surface contacting an electrical contact.

摘要翻译： 提供半导体器件中的自对准接触焊盘及其形成方法。 这些自对准接触焊盘可以增加接触焊盘的上表面以增加对准边缘。 栅极掩模的部分被切割，增加了栅极结构之间的空间。 结果，填充在这些空间中的接触垫具有与电接触接触的增加的上表面。

公开(公告)号：US06177320B1

公开(公告)日：2001-01-23

申请号：US09226961

申请日：1999-01-08

申请人： Chang-Hyun Cho ,  Hong-Sik Jeong ,  Jae-Goo Lee ,  Chang-Jin Kang ,  Sang-Sup Jeong ,  Chul Jung ,  Chan-Ouk Jung

发明人： Chang-Hyun Cho ,  Hong-Sik Jeong ,  Jae-Goo Lee ,  Chang-Jin Kang ,  Sang-Sup Jeong ,  Chul Jung ,  Chan-Ouk Jung

IPC分类号： H01L21336

CPC分类号： H01L27/10844 ,  H01L21/31144 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76897 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

摘要： A self aligned contact pad in a semiconductor device and a method for forming the self aligned contact pad are disclosed. A bit line contact pad and a storage node contact pad are simultaneously formed by using a photoresist layer pattern having a T-shaped opening including at least two contact regions. An etch stopping layer is formed over a semiconductor substrate and over a transistor. An interlayer dielectric layer is then formed over the etch stopping layer. Next, the interlayer dielectric layer is planarized to have a planar top surface. A mask pattern having a T-shaped opening is then formed over the interlayer dielectric layer, exposing the active region and a portion of the inactive region. The interlayer dielectric layer and etch stopping layer are sequentially etched to reveal a top surface of the semiconductor substrate using the mask pattern, thereby forming a self aligned contact opening exposing a top surface of the semiconductor substrate. The mask pattern is then removed. A conductive layer is formed in the self aligned contact opening and over the interlayer dielectric layer. The conductive layer and the interlayer dielectric layer are planarization-etched to reveal a top surface of the gate mask, thereby forming at least two contact pads.

摘要翻译： 公开了半导体器件中的自对准接触焊盘和用于形成自对准接触焊盘的方法。 通过使用具有包括至少两个接触区域的T形开口的光致抗蚀剂层图案，同时形成位线接触焊盘和存储节点接触焊盘。 在半导体衬底上并在晶体管上形成蚀刻停止层。 然后在蚀刻停止层上形成层间电介质层。 接下来，层间绝缘层被平坦化以具有平坦的顶表面。 然后在层间电介质层上形成具有T形开口的掩模图案，暴露有源区和一部分非活性区。 依次蚀刻层间电介质层和蚀刻停止层，以使用掩模图案露出半导体衬底的顶表面，从而形成暴露半导体衬底的顶表面的自对准接触开口。 然后去除掩模图案。 导电层形成在自对准接触开口中以及层间电介质层之上。 对导电层和层间电介质层进行平面蚀刻以露出栅极掩模的顶表面，从而形成至少两个接触焊盘。

公开(公告)号：US07701235B2

公开(公告)日：2010-04-20

申请号：US12098778

申请日：2008-04-07

申请人： Chang-Hyun Cho ,  Joon-Yeon Kim ,  Sang-Gu Kang ,  Sung-Mo Kang ,  Sang-Kyu Yoo

发明人： Chang-Hyun Cho ,  Joon-Yeon Kim ,  Sang-Gu Kang ,  Sung-Mo Kang ,  Sang-Kyu Yoo

IPC分类号： G01R31/02

CPC分类号： G01R31/2889 ,  G01R31/2891

摘要： Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.

摘要翻译： 具有用于探针卡的力接收图案和用于测试头的强制部件的基板测试探测设备及其使用方法，其中用于探针卡的受力图案和用于测试头的强制部件 当在高温和低温下测试半导体衬底时，可以抑制探针卡的热膨胀和收缩。 为此，制备具有基板移动器，探针卡和测试头的基板测试探测设备，其中测试头具有强制部分，探针卡具有受力板。 将半导体衬底放置在衬底移动器上以与探针卡电连接。 半导体衬底由探针卡和测试头电测试。 当半导体衬底被测试时，测试头的强制部分与探针卡的受力图案接触。

公开(公告)号：US5844914A

公开(公告)日：1998-12-01

申请号：US850807

申请日：1997-05-02

申请人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

发明人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/3181 ,  G11C11/406 ,  G11C29/08 ,  G11C29/12 ,  G11C29/18 ,  G06F11/00

CPC分类号： G11C29/18 ,  G01R31/31813

摘要： A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

摘要翻译： 示出了半导体存储器件和方法，其中内置系统测试（BIST）电路基于测试算法和DRAM存储单元阵列的刷新要求确定BIST电路执行刷新操作的刷新点地址 当测试地址到达刷新点地址时，在存储单元阵列中的测试数据。 还示出了半导体存储器件和方法的另一实施例，其中BIST电路在输入到存储器电路之前对测试地址和测试数据进行解扰，该存储器电路包括地址和数据加扰电路，使得逻辑测试地址和根据 测试算法与存储单元阵列中的物理地址和数据相匹配。