公开(公告)号：US07372102B2

公开(公告)日：2008-05-13

申请号：US11272259

申请日：2005-11-10

Applicant: Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

Inventor： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

IPC: H01L29/76

CPC classification number: H01L21/76232 ,  H01L21/763

Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.

Abstract translation: 提供一种具有用于半导体器件的浅沟槽 - 深沟槽隔离区域的结构。

公开(公告)号：US20070246691A1

公开(公告)日：2007-10-25

申请号：US11701806

申请日：2007-02-02

Applicant: Zhong-Wu Luo ,  Jun Lin ,  Lin Jian ,  Tie-Qiang Peng

Inventor： Zhong-Wu Luo ,  Jun Lin ,  Lin Jian ,  Tie-Qiang Peng

IPC: H01B1/12

CPC classification number: H01B1/122

Abstract: An electrolyte for anodizing magnesium products, includes a base solution, a main blackening agent, an auxiliary blackening agent, and a complexing agent. The base solution includes 2 to 25 g/l of alkali, 1 to 30 g/l of fluoride, and 1 to 35 g/l of silicate. The main blackening agent mainly includes cupric salt, concentration of the cupric salt is from 0.3 to 9 grams per liter (g/l). The auxiliary blackening agent mainly includes oxysalt, concentration of the oxysalt is from 0.1 to 8 g/l. Concentration of the complexing agent is from 0.5 to 20 g/l.

Abstract translation: 用于阳极氧化镁产品的电解质包括碱溶液，主要黑化剂，辅助黑化剂和络合剂。 碱溶液包括2至25g / l的碱，1至30g / l的氟化物和1至35g / l的硅酸盐。 主要的黑化剂主要包括铜盐，铜盐的浓度为0.3〜9克/升（g / l）。 辅助黑化剂主要包括氧化钾，氧化锡的浓度为0.1〜8g / l。 络合剂的浓度为0.5〜20g / l。

公开(公告)号：US20070101037A1

公开(公告)日：2007-05-03

申请号：US11260054

申请日：2005-10-27

Applicant: Jun Lin ,  Thomas Wright

Inventor： Jun Lin ,  Thomas Wright

IPC: H05K7/10

CPC classification number: G06F1/185

Abstract: A connecting apparatus comprises a riser card (10) and a slot (20). The riser card comprises a PCI-X slot (13), a PCI-E slot (11), a first connector (15), a second connector (17) and a third connector (19). The first connector set a serial of PCI-X signal pads (151) on one side thereof. The second connector is adapted to provide power and ground signals. The third connector set a serial of PCI-E signal pads (191) on the same side thereof as the first connector. The slot is defined on a circuit board for the riser card inserted therein. The slot comprises a first portion (21) and a second portion (23) coupling to the second connector. The first portion comprises a first side with a series of PCI-X signal pins (211) coupling to the serial of PCI-X signal pads of the first connector, when the riser card is inserted into the slot in a first direction with the first connector inserted into the first portion. The first portion comprises a second side with a series of PCI-E signal pins (191) coupling to the serial of PCI-E signal pads of the third connector, when the riser card is inserted into the slot in a second direction which is reverse to the first direction with the third connector inserted into the second portion.

Abstract translation: 连接装置包括转接卡（10）和槽（20）。 转接卡包括PCI-X插槽（13），PCI-E插槽（11），第一连接器（15），第二连接器（17）和第三连接器（19）。 第一连接器在其一侧上设置一系列PCI-X信号焊盘（151）。 第二连接器适于提供电源和接地信号。 第三连接器在与第一连接器相同的一侧设置一系列PCI-E信号焊盘（191）。 插槽定义在插入其中的转接卡的电路板上。 狭槽包括第一部分（21）和联接到第二连接器的第二部分（23）。 第一部分包括具有连接到第一连接器的PCI-X信号焊盘串联的一系列PCI-X信号引脚（211）的第一侧，当转接卡沿第一方向插入到槽中时，第一 连接器插入第一部分。 第一部分包括具有连接到第三连接器的PCI-E信号焊盘系列的一系列PCI-E信号引脚（191）的第二侧，当转接卡沿第二方向插入到槽中时 到第一方向，第三连接器插入第二部分。

公开(公告)号：US07144631B2

公开(公告)日：2006-12-05

申请号：US10703641

申请日：2003-11-07

Applicant: Jun Lin ,  Leatrese Dionne Hopkins ,  David M. Zukowski ,  Scott W. Loper

Inventor： Jun Lin ,  Leatrese Dionne Hopkins ,  David M. Zukowski ,  Scott W. Loper

IPC: B32B27/40 ,  B32B27/38 ,  B32B27/26 ,  B05D1/36

CPC classification number: B05D7/53 ,  Y10T428/31515 ,  Y10T428/31551 ,  Y10T428/31663

Abstract: A method for adhering windshield sealants directly over a basecoat/clearcoat finish in which the clearcoat comprises a carbamate polymer or oligomer.

Abstract translation: 一种用于将挡风玻璃密封剂直接粘附在底漆/透明涂层上的方法，其中透明涂层包含氨基甲酸酯聚合物或低聚物。

公开(公告)号：US07015086B2

公开(公告)日：2006-03-21

申请号：US10772940

申请日：2004-02-05

Applicant: Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

Inventor： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

IPC: H01L21/8238

CPC classification number: H01L21/76232 ,  H01L21/763

Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.

Abstract translation: 已经开发了用于形成由浅沟槽 - 深沟槽构造构成的隔离区域的工艺，其中获得用于隔离区域和半导体衬底中的相邻有源器件区域的平滑顶表面形貌。 该工艺特征最初形成通过第一化学机械抛光工艺平坦化的绝缘体填充的浅沟槽形状，允许在随后形成在绝缘体填充的浅沟槽形状中的窄直径，深沟槽开口期间实现降低的复杂性 半导体衬底的下面部分。 位于深沟槽开口底部的凹陷多晶硅插塞的形成之后，形成位于深沟槽开口的顶部的绝缘体塞，覆盖凹入的多晶硅插塞。 这通过光刻和选择性干法定义程序和第二化学机械抛光程序来实现，从而产生填充的深沟槽开口，表现出光滑的顶表面形貌。

公开(公告)号：US20050282089A1

公开(公告)日：2005-12-22

申请号：US11201891

申请日：2005-08-11

Applicant: Chen-Kuei Chung ,  Chun-Jun Lin ,  Chung-Chu Chen

Inventor： Chen-Kuei Chung ,  Chun-Jun Lin ,  Chung-Chu Chen

IPC: B41J2/14 ,  B41J2/16

CPC classification number: B41J2/1645 ,  B41J2/14129 ,  B41J2/14145 ,  B41J2/1603 ,  B41J2/1625 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1642 ,  B41J2/1643 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49401

Abstract: A method for fabricating a thermal inkjet head equipped with a symmetrical heater and the head fabricated by the method are provided. The method incorporates two thick photoresist deposition processes and a nickel electroplating process. The first thick photoresist deposition process is carried out to form an ink chamber in fluid communication with a funnel-shaped manifold and an injector orifice. The second thick photoresist deposition process forms a mold for forming an injector passageway that leads to the injector orifice. The nickel electroplating process provides an orifice plate on top of the inkjet head through which an injector passageway that leads to the injector orifice is provided for injecting ink droplets.

Abstract translation: 提供一种制造配备有对称加热器的热喷墨头和通过该方法制造的头的方法。 该方法包括两个厚的光致抗蚀剂沉积工艺和镍电镀工艺。 进行第一厚的光致抗蚀剂沉积工艺以形成与漏斗形歧管和喷射器孔流体连通的墨室。 第二厚的光致抗蚀剂沉积工艺形成用于形成通向喷射孔的喷射器通道的模具。 镍电镀工艺在喷墨头的顶部提供孔板，通过该孔板提供通向喷射器孔口的喷射器通道用于喷射墨滴。

公开(公告)号：US20050176214A1

公开(公告)日：2005-08-11

申请号：US10772940

申请日：2004-02-05

Applicant: Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

Inventor： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L21/76232 ,  H01L21/763

Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.

Abstract translation: 已经开发了用于形成由浅沟槽 - 深沟槽构造构成的隔离区域的工艺，其中获得用于隔离区域和半导体衬底中的相邻有源器件区域的平滑顶表面形貌。 该工艺特征最初形成通过第一化学机械抛光工艺平坦化的绝缘体填充的浅沟槽形状，允许在随后形成在绝缘体填充的浅沟槽形状中的窄直径，深沟槽开口期间实现降低的复杂性 半导体衬底的下面部分。 位于深沟槽开口底部的凹陷多晶硅插塞的形成之后，形成位于深沟槽开口的顶部的绝缘体塞，覆盖凹入的多晶硅插塞。 这通过光刻和选择性干法定义程序和第二化学机械抛光程序来实现，从而产生填充的深沟槽开口，表现出光滑的顶表面形貌。

公开(公告)号：US06795344B2

公开(公告)日：2004-09-21

申请号：US10316851

申请日：2002-12-12

Applicant: Yeh Jun Lin

Inventor： Yeh Jun Lin

IPC: G11C1610

CPC classification number: G11C16/30

Abstract: A floating gate memory architecture having current regulator is disclosed. A floating gate memory block have at least a programming voltage node for being programmed a plurality of bits according to the control of a plurality of bit lines. A high voltage source provides a regulated voltage when the plurality of bits are programmed in. A high voltage decoder locates between the floating gate memory block and the high voltage source for connecting the voltage to the programming voltage node according to the programming data of the floating gate memory block. A current regulator connects to the programming voltage node for keeping the programming voltage node in a constant voltage, and making a constant current flowing into said floating gate memory block according to said plurality of bits.

Abstract translation: 公开了一种具有电流调节器的浮动存储架构。 浮动栅极存储块至少具有编程电压节点，用于根据多个位线的控制来编程多个位。 当多个位被编程时，高电压源提供调节电压。高电压解码器位于浮动栅极存储器块和高电压源之间，用于根据浮动的编程数据将电压连接到编程电压节点 门内存块。 电流调节器连接到编程电压节点，用于将编程电压节点保持在恒定电压，并根据所述多个位使恒定电流流入所述浮动栅极存储器块。

公开(公告)号：US06747336B2

公开(公告)日：2004-06-08

申请号：US09804389

申请日：2001-03-13

Applicant: Jun-Lin Tsai ,  Ruey-Hsing Liu ,  Chiou-Shian Peng ,  Kuo-Chio Liu

Inventor： Jun-Lin Tsai ,  Ruey-Hsing Liu ,  Chiou-Shian Peng ,  Kuo-Chio Liu

IPC: H01L27082

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/732

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract translation: 描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。 所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。 本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。 为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。

公开(公告)号：US06707717B2

公开(公告)日：2004-03-16

申请号：US10214120

申请日：2002-08-08

Applicant: Yeh Jun-Lin

Inventor： Yeh Jun-Lin

IPC: G11C1606

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C2207/063

Abstract: A current sense amplifier with dynamic pre-charge is proposed. There is a storage unit having a sense line, a voltage amplifier for generating a first output signal depending on the sense line, a first current mirror for generating a first current depending on the first output signal, a second current mirror for generating a second current depending on a reference storage unit, and a pre-charge circuit for generating a charge up signal on the sense line to pre-charge the sense line to an operation current level depending on the first output signal, the second current and a clock pulse so as to directly detect a data in the storage unit during detecting the sense line.

Abstract translation: 提出了具有动态预充电的电流检测放大器。 存在具有检测线的存储单元，用于根据检测线产生第一输出信号的电压放大器，用于根据第一输出信号产生第一电流的第一电流镜，用于产生第二电流的第二电流镜 取决于参考存储单元，以及预充电电路，用于在感测线上产生充电信号，以根据第一输出信号，第二电流和时钟脉冲将感测线预充电到工作电流电平 以便在检测感测线期间直接检测存储单元中的数据。