公开(公告)号：US07195970B2

公开(公告)日：2007-03-27

申请号：US10811409

申请日：2004-03-26

申请人： Kuo-Chi Tu ,  Wai-Yi Lien

发明人： Kuo-Chi Tu ,  Wai-Yi Lien

IPC分类号： H01L27/148

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/65

摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.

摘要翻译： 提供金属绝缘体金属（MIM）电容器。 MIM电容器的底部电极电连接到连接节点。 连接节点可以是例如形成在层间电介质中的接触，多晶硅连接节点，掺杂多晶硅或硅区域等。 触点提供连接节点和形成在连接节点上方的组件之间的电连接。 第二触点提供与顶部电极的电连接。

公开(公告)号：US07115935B2

公开(公告)日：2006-10-03

申请号：US10822197

申请日：2004-04-09

申请人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Huey-Chi Chu

发明人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Huey-Chi Chu

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10811 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

摘要： A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.

摘要翻译： 描述了在嵌入式DRAM工艺中制造金属 - 绝缘体 - 金属电容器的方法。 多个接触插塞通过绝缘层提供到衬底中的半导体器件结构，其中接触插塞形成在衬底的逻辑区域中并且在衬底的存储区域中并且将节点接触插塞提供到衬底内的节点接触区域 底物在记忆区。 此后，电容器在自对准铜工艺中以扭曲的沟槽制造。

公开(公告)号：US07071509B2

公开(公告)日：2006-07-04

申请号：US11040039

申请日：2005-01-21

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L21/0276 ,  H01L27/10861 ,  H01L27/10891 ,  H01L27/11

摘要： A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlying the stress-balancing layer. The stack is patterned to form the capacitors. Gate transistors are formed overlying the capacitors wherein the stress-balancing layer prevents formation of stress-induced voids during the thermal processes involved in forming the gate transistors.

摘要翻译： 描述了一种制造具有不具有应力诱发空隙的上覆晶体管的电容器的方法。 覆盖在基板上的电容器叠层被提供。 叠层堆叠应力平衡介电层。 沉积在应力平衡层上的抗反射涂层（ARC）层。 图案化堆叠以形成电容器。 形成覆盖电容器的栅极晶体管，其中应力平衡层在形成栅极晶体管的热处理期间阻止形成应力诱发的空隙。

公开(公告)号：US07030444B2

公开(公告)日：2006-04-18

申请号：US10786798

申请日：2004-02-25

申请人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

发明人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.

摘要翻译： 公开了一种用于防止反向隧道的分裂门闪存单元结构。 在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。 浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。 侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层， 浮栅绝缘体层。 栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。 导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

公开(公告)号：US20060017115A1

公开(公告)日：2006-01-26

申请号：US10896491

申请日：2004-07-22

申请人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Chung-Yi Chen ,  C. Shen ,  Chun-Yao Chen ,  Hsiang-Fan Lee

发明人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Chung-Yi Chen ,  C. Shen ,  Chun-Yao Chen ,  Hsiang-Fan Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/10861 ,  H01L27/10873

摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

摘要翻译： 与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。 栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

公开(公告)号：US20050258512A1

公开(公告)日：2005-11-24

申请号：US10851572

申请日：2004-05-21

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/00 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L23/5223 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10897 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic product includes a capacitor structure spaced from a contact region within a substrate by a conductor stud layer and an interconnect layer formed upon the conductor stud layer. The interconnect layer may be further spaced from the capacitor structure by a contiguous conductor interconnect and conductor stud layer. The use of the interconnect layer and the contiguous conductor interconnect and conductor stud layer provide for flexible placement of the capacitor structure within the microelectronic product.

摘要翻译： 微电子产品包括通过导体柱层与衬底内的接触区域间隔开的电容器结构，以及形成在导体柱层上的互连层。 互连层可以通过连续的导体互连和导体柱层与电容器结构进一步间隔开。 使用互连层和连续导体互连和导体柱层提供电容器结构在微电子产品内的柔性放置。

公开(公告)号：US20050212021A1

公开(公告)日：2005-09-29

申请号：US10811409

申请日：2004-03-26

申请人： Kuo-Chi Tu ,  Wai-Yi Lien

发明人： Kuo-Chi Tu ,  Wai-Yi Lien

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/65

摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.

摘要翻译： 提供金属绝缘体金属（MIM）电容器。 MIM电容器的底部电极电连接到连接节点。 连接节点可以是例如形成在层间电介质中的接触，多晶硅连接节点，掺杂多晶硅或硅区域等。 触点提供连接节点和形成在连接节点上方的组件之间的电连接。 第二触点提供与顶部电极的电连接。

公开(公告)号：US20050124132A1

公开(公告)日：2005-06-09

申请号：US11031717

申请日：2005-01-07

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20 ,  H01L21/311

CPC分类号： H01L27/10888 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10897 ,  H01L28/91

摘要： A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive material layers. The first conductive material layer coats an inside surface of a cup-shaped opening formed in an insulating layer. The trench is formed in the insulating layer. The trench extends between and crosses each of the capacitors in the group. The dielectric layer and the second conductive material layer are formed over the first conductive material layer in the cup-shaped openings and over an inside surface of the trench. The second conductive material layer extends between the capacitors of the group via the trench. Also, the second conductive material layer forms top electrodes for the capacitors of the group.

摘要翻译： 半导体器件包括一组电容器和沟槽。 每个电容器包括第一导电材料层，电介质层和第二导电材料层。 电介质层位于第一和第二导电材料层之间。 第一导电材料层涂覆形成在绝缘层中的杯形开口的内表面。 沟槽形成在绝缘层中。 沟槽在组中每个电容器之间延伸并交叉。 电介质层和第二导电材料层形成在杯形开口中的第一导电材料层上方和沟槽的内表面之上。 第二导电材料层经由沟槽在组的电容器之间延伸。 此外，第二导电材料层形成用于该组的电容器的顶部电极。

公开(公告)号：US06867129B2

公开(公告)日：2005-03-15

申请号：US10618793

申请日：2003-07-15

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/4763

CPC分类号： H01L28/60 ,  H01L21/0276 ,  H01L27/10861 ,  H01L27/10891 ,  H01L27/11

摘要： A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlying the stress-balancing layer. The stack is patterned to form the capacitors. Gate transistors are formed overlying the capacitors wherein the stress-balancing layer prevents formation of stress-induced voids during the thermal processes involved in forming the gate transistors.

摘要翻译： 描述了一种制造具有不具有应力诱发空隙的上覆晶体管的电容器的方法。 覆盖在基板上的电容器叠层被提供。 叠层堆叠应力平衡介电层。 沉积在应力平衡层上的抗反射涂层（ARC）层。 图案化堆叠以形成电容器。 形成覆盖电容器的栅极晶体管，其中应力平衡层在形成栅极晶体管的热处理期间阻止形成应力诱导的空隙。

公开(公告)号：US06486033B1

公开(公告)日：2002-11-26

申请号：US09808927

申请日：2001-03-16

申请人： Kuo-Chi Tu ,  Wan-Yih Lieh

发明人： Kuo-Chi Tu ,  Wan-Yih Lieh

IPC分类号： H01L218234

CPC分类号： H01L21/76897 ,  H01L27/10873 ,  H01L27/10894

摘要： A method for forming logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate separating at least one logic area and at least one memory area. Gate electrode stacks comprising a polysilicon layer, a silicide layer, a first oxide layer, and a first nitride layer are formed in the device areas. The semiconductor substrate and the gate electrode stacks are covered with a first mask. The first mask in the logic areas is partially removed to expose the first nitride layer. The first nitride layer is removed to expose the first oxide layer in the logic areas. The first mask is removed. Processing continues to form LDD regions, S/D regions in the logic areas, and memory devices in the memory areas. Since the first nitride layer in the logic areas has been removed, an etching with an etch stop at nitride can form metal contacts in the logic areas and memory areas simultaneously. No substrate loss is seen in the S/D region of the logic areas and metal shorting of the contact to the gate is avoided even with mask misalignment because of the etch stop at the nitride in the memory area.

摘要翻译： 描述了一种用嵌入式存储器形成逻辑电路的方法。 隔离区形成在分离至少一个逻辑区域和至少一个存储区域的半导体衬底上。 在器件区域中形成包括多晶硅层，硅化物层，第一氧化物层和第一氮化物层的栅电极堆叠。 半导体衬底和栅极电极堆叠被第一掩模覆盖。 部分去除逻辑区域中的第一掩模以露出第一氮化物层。 去除第一氮化物层以露出逻辑区域中的第一氧化物层。 第一个面具被删除。 处理继续形成LDD区域，逻辑区域中的S / D区域以及存储区域中的存储器件。 由于逻辑区域中的第一氮化物层已被去除，所以在氮化物处的蚀刻停止的蚀刻可以在逻辑区域和存储区域中同时形成金属接触。 在逻辑区域的S / D区域中没有看到衬底损耗，并且由于在存储区域中的氮化物处的蚀刻停止，即使采用掩模未对准也避免了与栅极的接触的金属短路。