Abstract:
One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.
Abstract:
In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.
Abstract:
At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.
Abstract:
Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.
Abstract:
The present invention relates to an acrylic impact modifier having a multilayered structure, which offers both superior impact resistance and coloring characteristics to engineering plastics, such as polycarbonate (PC) and a polycarbonate/polybutylene terephthalate alloy resin, or to a polyvinyl chloride resin. The present invention provides an acrylic impact modifier having a multilayered structure comprising: a) a seed prepared by emulsion copolymerization of a vinylic monomer and a hydrophilic monomer; b) a rubbery core surrounding the seed and comprising a C2 to C8 alkyl acrylate polymer, and c) a shell surrounding the rubbery core and comprising a C1, to C4 alkyl methacrylate polymer, a method for preparing the same, and a thermoplastic resin comprising the same.
Abstract:
In various methods of performing program operations in phase change memory devices, selected memory cells are repeatedly programmed to obtain resistance distributions having desired characteristics such as adequate sensing margins.
Abstract:
In one aspect, a non-volatile memory includes a phase-change memory cell array which includes a plurality of normal phase-change memory cells and a plurality of pseudo one-time-programmable (OTP) phase-change memory cells, a write driver which writes data into the normal and pseudo OTP phase-change memory cells of the phase-change memory cell array, and an OTP controller which selectively disables the write driver.
Abstract:
The present invention provides a method of manufacturing an aromatic polyamide composite membrane comprising: coating an aqueous solution containing polyfunctional aromatic amine to a porous polymer substrate; and reacting the coated substrate with an organic solution containing polyfunctional aromatic acyl halide to lead to interfacial condensation polymerization between the polyfunctional aromatic amine and the polyfunctional aromatic acyl halide so that the reaction product resulting from the interfacial condensation polymerization is coated on the surface of the substrate, characterized in that either of the aqueous solution containing polyfunctional aromatic amine or the organic solution containing polyfunctional aromatic acyl halide has dendritic polymer as one of polyfunctional compounds added thereto. The resulting aromatic polyamide composite membrane which includes dendrimer as polyfunctional compound, exhibits high salt rejection rate and water flux.
Abstract:
A resistive memory device includes a memory core unit and a buffer memory for reducing overhead of a memory controller in a memory system. The buffer memory stores input data associated with a write command. The memory core unit includes resistive memory cells for storing the input data from the buffer memory. The buffer memory is comprised of a different type of memory cells from the resistive memory cells such that the different type of memory cells writes the input data with a faster speed than the resistive memory cells.
Abstract:
A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher than the first voltage and supplies a firing pulse to at least one firing-failed phase change memory cell.