公开(公告)号：US20080199619A1

公开(公告)日：2008-08-21

申请号：US12063070

申请日：2006-08-08

申请人： Jae Hee Ryu ,  Sung Hak Choi ,  Kwang Jin Lee

发明人： Jae Hee Ryu ,  Sung Hak Choi ,  Kwang Jin Lee

IPC分类号： B05D3/10

CPC分类号： C08J5/2275 ,  C08J2300/202

摘要： The present invention provides a method of manufacturing an aromatic polyamide composite membrane comprising: coating an aqueous solution containing polyfunctional aromatic amine to a porous polymer substrate; and reacting the coated substrate with an organic solution containing polyfunctional aromatic acyl halide to lead to interfacial condensation polymerization between the polyfunctional aromatic amine and the polyfunctional aromatic acyl halide so that the reaction product resulting from the interfacial condensation polymerization is coated on the surface of the substrate, characterized in that either of the aqueous solution containing polyfunctional aromatic amine or the organic solution containing polyfunctional aromatic acyl halide has dendritic polymer as one of polyfunctional compounds added thereto. The resulting aromatic polyamide composite membrane which includes dendrimer as polyfunctional compound, exhibits high salt rejection rate and water flux.

摘要翻译： 本发明提供了一种制备芳族聚酰胺复合膜的方法，包括：将多官能芳族胺的水溶液涂布到多孔聚合物基材上; 并使涂覆的基材与含有多官能芳族酰卤的有机溶液反应，导致多官能芳族胺和多官能芳族酰卤之间的界面缩聚，从而将界面缩聚产生的反应产物涂覆在基材表面上 其特征在于，含有多官能芳香族胺的水溶液或含有多官能芳香族酰卤的有机溶液中的任一种都具有树枝状聚合物作为添加多官能化合物之一。 得到的芳香族聚酰胺复合膜，其包含作为多官能化合物的树枝状大分子，显示出高的脱盐率和水通量。

公开(公告)号：US20130265837A1

公开(公告)日：2013-10-10

申请号：US13710504

申请日：2012-12-11

申请人： Yong Jin Kwon ,  Kwang Jin Lee ,  Hye-Jin Kim

发明人： Yong Jin Kwon ,  Kwang Jin Lee ,  Hye-Jin Kim

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0088

摘要： A non-volatile memory device includes a set pulse generator configured to generate a set pulse, a reset pulse generator configured to generate a reset pulse based on the set pulse, and a write driver block configured to write second data to a second non-volatile memory cell using the reset pulse, while writing first data to a first non-volatile memory cell using the set pulse.

摘要翻译： 非易失性存储器件包括被配置为产生置位脉冲的置位脉冲发生器，被配置为基于所设置的脉冲产生复位脉冲的复位脉冲发生器，以及被配置为将第二数据写入第二非易失性的写入驱动器块 使用复位脉冲的存储单元，同时使用设定脉冲将第一数据写入第一非易失性存储单元。

公开(公告)号：US07881145B2

公开(公告)日：2011-02-01

申请号：US12453872

申请日：2009-05-26

申请人： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

发明人： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

IPC分类号： G11C8/00

CPC分类号： G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

摘要： A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

摘要翻译： 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

公开(公告)号：US20100131708A1

公开(公告)日：2010-05-27

申请号：US12292896

申请日：2008-11-28

申请人： Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

发明人： Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

IPC分类号： G06F12/00

CPC分类号： G11C13/0069 ,  G11C15/046 ,  G11C2013/0076

摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address.

摘要翻译： 在一个实施例中，半导体器件包括非易失性存储器单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器，以及写入地址缓冲器，被配置为存储与存储的每个数据相关联的写入地址 在写缓冲区。 输出电路被配置为选择性地输出从非易失性存储器阵列读取的数据和来自写入缓冲器的数据之一。 旁路控制电路被配置为基于输入读取地址是否匹配存储在写入地址缓冲器中的有效写入地址来控制输出电路。 如果所存储的写入地址与输入写入地址相匹配，则无效单元被配置为使存储在写入地址缓冲器中的地址无效。

公开(公告)号：US20080197071A1

公开(公告)日：2008-08-21

申请号：US12063078

申请日：2006-08-08

申请人： Moo Seok Lee ,  Kwang Jin Lee

发明人： Moo Seok Lee ,  Kwang Jin Lee

IPC分类号： B01D71/56 ,  B29C47/06

CPC分类号： B01D61/027 ,  B01D69/02 ,  B01D69/085 ,  B01D69/087 ,  B01D69/12 ,  B01D71/56 ,  B01D2325/24 ,  B01D2325/40

摘要： Disclosed are a nanofiltration composite hollow fiber membrane and a method of manufacturing the same. The nanofiltration composite hollow fiber membrane includes a reinforcement (1) which is a tubular braid, a polymeric resin thin film (2) coated on the outer surface of the reinforcement (1), and a polyamide active layer (3) formed on the outer surface of the polymeric resin thin film. The present invention has an advantage of an excellent strength and an increase in membrane area relative to an installation area.

摘要翻译： 公开了一种纳滤复合中空纤维膜及其制造方法。 纳滤复合中空纤维膜包括：管状编织物的加强件（1），涂覆在加强件（1）的外表面上的聚合物树脂薄膜（2）和形成在外部的聚酰胺活性层（3） 聚合物树脂薄膜的表面。 本发明具有相对于安装面积优异的强度和膜面积的增加的优点。

公开(公告)号：US06459652B1

公开(公告)日：2002-10-01

申请号：US09996225

申请日：2001-11-28

申请人： Jong Cheol Lee ,  Kwang Jin Lee

发明人： Jong Cheol Lee ,  Kwang Jin Lee

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C29/14

摘要： A semiconductor memory device effectively capable of removing skew between data output of a data output circuit and an echo clock of an echo clock generator is provided. The semiconductor memory device comprises a delay circuit comprising a plurality of delay paths for delaying the data enable clock by different time, a test controller for generating a mode select signal and a delay path test signal in response to a test code signal, and a delay signal selection circuit comprising a plurality of fuses for producing a default delay path select signal based on a programmed state of the plurality of fuses, and a multiplexer, responsive to the mode select signal, for selectively providing the default delay path select signal or the delay path test signal to the delay circuit.

摘要翻译： 提供了有效地消除数据输出电路的数据输出与回波时钟发生器的回波时钟之间的偏差的半导体存储器件。 半导体存储器件包括延迟电路，该延迟电路包括多个用于将数据使能时钟延迟不同时间的延迟路径，用于响应于测试代码信号产生模式选择信号和延迟路径测试信号的测试控制器以及延迟 信号选择电路，包括多个保险丝，用于基于多个保险丝的编程状态产生默认延迟路径选择信号;以及复用器，响应于模式选择信号，用于选择性地提供默认延迟路径选择信号或延迟 路径测试信号到延迟电路。

公开(公告)号：US20140191443A1

公开(公告)日：2014-07-10

申请号：US14233424

申请日：2011-12-09

申请人： Hyun Kuk Park ,  Ik Hyun Oh ,  Hee Jun Yoon ,  Hyeon Taek Son ,  Kwang Jin Lee ,  Hee Seon Bang ,  Han Sur Bang

发明人： Hyun Kuk Park ,  Ik Hyun Oh ,  Hee Jun Yoon ,  Hyeon Taek Son ,  Kwang Jin Lee ,  Hee Seon Bang ,  Han Sur Bang

IPC分类号： C04B35/64 ,  C04B35/56 ,  B23K20/12

CPC分类号： C04B35/64 ,  B22F3/105 ,  B23K20/1245 ,  C04B35/5626 ,  C04B35/645 ,  C04B2235/6562 ,  C04B2235/6581 ,  C04B2235/666 ,  C04B2235/77 ,  C04B2235/96 ,  C22C29/08

摘要： The present invention relates to a preparation method of a tungsten carbide sintered body for a friction stir welding tool used in a friction stir welding tool of a high melting point material such as steel, titanium and the like or a dissimilar material such as aluminum, magnesium-steel, titanium and the like using pulsed current activation through a discharge plasma sintering apparatus. The preparation method comprises the following steps: filling a tungsten carbide (WC) powder in a mold made of a graphite material; mounting the mold filled with tungsten carbide powder in a chamber of a discharge plasma sintering apparatus; making a vacuum inside of the chamber; molding the tungsten carbide powder while maintaining a constant pressure inside the mold and increasing the temperature according to a set heat increase pattern until the temperature reaches a final target temperature; and cooling the inside of the chamber while maintaining the pressure pressurized in the mold after the molding step. According to the preparation method of a tungsten carbide sintered body for a friction stir welding tool, it is possible to obtain a high relative density of 99.5% or higher, and to prepare a uniform sintered body having a homogeneous tissue with little particle growth, high toughness, high abrasion resistance and high strength within a short time by a single process when preparing a tungsten carbide sintered body appropriate for a friction stir welding tool by using pulsed current activation through a discharge plasma sintering apparatus. In addition, since a sintered body is prepared with only a tungsten carbide single material, excluding a sintering additive such as cobalt, a preparation method is simplified, preparation costs are reduced, and toughness, abrasion resistance and strength are superior compared with a sintered body containing cobalt, a sintering additive.

摘要翻译： 本发明涉及一种用于摩擦搅拌焊接工具的碳化钨烧结体的制备方法，该工具用于诸如钢，钛等的高熔点材料的摩擦搅拌焊接工具或诸如铝，镁之类的异种材料 钢，钛等，通过放电等离子体烧结装置进行脉冲电流激活。 该制备方法包括以下步骤：在由石墨材料制成的模具中填充碳化钨（WC）粉末; 将填充有碳化钨粉末的模具安装在放电等离子体烧结装置的腔室中; 在室内进行真空; 在模具内保持恒定压力的同时成型碳化钨粉末，并根据设定的热量增加模式增加温度，直到温度达到最终目标温度; 并且在模制步骤之后保持在模具中加压的压力同时冷却腔室的内部。 根据用于摩擦搅拌焊接工具的碳化钨烧结体的制备方法，可以获得99.5％以上的高相对密度，并且制备均匀的具有少量颗粒生长的均匀组织的烧结体，高 当通过使用脉冲电流激活通过放电等离子体烧结装置制备适用于摩擦搅拌焊接工具的碳化钨烧结体时，通过单一工艺在短时间内具有韧性，高耐磨性和高强度。 此外，由于仅使用碳化钨单一材料制成烧结体，不包括钴等烧结添加剂，因此制备方法简单，制备成本降低，韧性，耐磨耗性和强度高于烧结体 含钴，烧结添加剂。

公开(公告)号：US08588010B2

公开(公告)日：2013-11-19

申请号：US12929349

申请日：2011-01-18

申请人： Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

发明人： Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

IPC分类号： G11C7/22

CPC分类号： G11C13/0064 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C15/00 ,  G11C2013/0078 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

摘要： At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

公开(公告)号：US08223527B2

公开(公告)日：2012-07-17

申请号：US12289937

申请日：2008-11-07

申请人： Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

发明人： Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/72

摘要： In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

摘要翻译： 在一个实施例中，半导体器件包括非易失性存储单元阵列，以及控制单元，被配置为产生指示闪光模式是否被使能的模式信号。 写电路被配置为基于模式信号写入非易失性存储单元阵列，使得如果闪存模式尚未被使能，则写电路禁止擦除非易失性存储单元阵列，并且指令擦除一个或多个单元 接收非易失性存储单元阵列。

公开(公告)号：US07978539B2

公开(公告)日：2011-07-12

申请号：US12292891

申请日：2008-11-28

申请人： Kwang Jin Lee ,  Byung Gil Choi

发明人： Kwang Jin Lee ,  Byung Gil Choi

IPC分类号： G11C7/22

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C15/00 ,  G11C15/046 ,  G11C2013/0076

摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.

摘要翻译： 在一个实施例中，半导体器件包括非易失性存储单元阵列。 非易失性存储单元阵列的存储单元是基于电阻的，并且每个存储单元具有在将数据写入存储单元之后随时间而改变的电阻。 写地址缓冲器被配置为存储与被写入非易失性存储单元阵列的数据相关联的写地址，并且读单元被配置为执行读操作以从非易失性存储单元阵列读取数据。 读取单元被配置为基于读取地址是否匹配所存储的写入地址之一和写入的数据的建立时间的至少一个指示来控制在读取操作期间施加到非易失性存储器单元阵列的读取电流 非易失性存储单元阵列。