公开(公告)号：US20210407040A1

公开(公告)日：2021-12-30

申请号：US17361783

申请日：2021-06-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Julien Closs ,  Jean-Michel Delorme ,  Daniel Fauvarque ,  Laurent Folliot ,  Guillaume Legrain

IPC: G06T3/40

Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.

公开(公告)号：US20210398919A1

公开(公告)日：2021-12-23

申请号：US17466941

申请日：2021-09-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Denis FARISON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/528 ,  H01L25/065

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

公开(公告)号：US11204739B2

公开(公告)日：2021-12-21

申请号：US16599581

申请日：2019-10-11

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Mark Wallis ,  Yannick Sebillet

IPC: G06F7/544 ,  G06F17/14 ,  G06F17/16

Abstract: A microcontroller is capable of executing a process that is parameterizable by at least one parameter. The microcontroller includes a processor and a hardware module coupled to the processor. The hardware module is configured to hardware execute the process and the processor is configured to deliver the at least one parameter to the hardware module.

公开(公告)号：US20210384903A1

公开(公告)日：2021-12-09

申请号：US17411838

申请日：2021-08-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Laurent Lopez

IPC: H03K17/687 ,  H03K17/30

Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

公开(公告)号：US11189360B2

公开(公告)日：2021-11-30

申请号：US16669184

申请日：2019-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jean-Michel Gril-Maffre ,  Christophe Eva

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/06

Abstract: A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.

公开(公告)号：US20210367619A1

公开(公告)日：2021-11-25

申请号：US17394118

申请日：2021-08-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice ROMAIN ,  Mathieu LISART ,  Patrick ARNOULD

IPC: H03M13/29 ,  G06F11/10

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

公开(公告)号：US11183505B2

公开(公告)日：2021-11-23

申请号：US16939603

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L27/11531 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/311 ,  H01L27/11521

Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.

公开(公告)号：US20210342265A1

公开(公告)日：2021-11-04

申请号：US17229161

申请日：2021-04-13

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Laurent Folliot ,  Emanuele Plebani ,  Mirko Falchetto

IPC: G06F12/06 ,  G06N3/04

Abstract: According to one aspect, a method for determining, for a memory allocation, placements in a memory area of data blocks generated by a neural network, comprises a development of an initial sequence of placements of blocks, each placement being selected from several possible placements, the initial sequence being defined as a candidate sequence, a development of at least one modified sequence of placements from a replacement of a given placement of the initial sequence by a memorized unselected placement, and, if the planned size of the memory area obtained by this modified sequence is less than that of the memory area of the candidate sequence, then this modified sequence becomes the candidate sequence, the placements of the blocks for the allocation being those of the placement sequence defined as a candidate sequence once each modified sequence has been developed.

公开(公告)号：US20210319836A1

公开(公告)日：2021-10-14

申请号：US17224024

申请日：2021-04-06

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Enrico CASTALDO ,  Francesca GRANDE ,  Santi Nunzio Antonino PAGANO ,  Giuseppe NASTASI ,  Franco ITALIANO

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11529

Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.

公开(公告)号：US11143701B2

公开(公告)日：2021-10-12

申请号：US16909696

申请日：2020-06-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.