公开(公告)号：US20130082242A1

公开(公告)日：2013-04-04

申请号：US13251637

申请日：2011-10-03

Applicant: Shu-Jen Han ,  Alberto Valdes Garcia

Inventor： Shu-Jen Han ,  Alberto Valdes Garcia

IPC: H01L29/772 ,  H01L21/336 ,  H01L29/775 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/66742 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78636 ,  H01L29/78684

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

公开(公告)号：US08309418B2

公开(公告)日：2012-11-13

申请号：US12860977

申请日：2010-08-23

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66621

Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

Abstract translation: 场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料， 填充空腔的金属栅极材料，源极区域和漏极区域。

公开(公告)号：US08106455B2

公开(公告)日：2012-01-31

申请号：US12432927

申请日：2009-04-30

Applicant: Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

Inventor： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract translation: 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US20100276753A1

公开(公告)日：2010-11-04

申请号：US12432927

申请日：2009-04-30

Applicant: Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

Inventor： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC: H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8236

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract translation: 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US20090317915A1

公开(公告)日：2009-12-24

申请号：US12453700

申请日：2009-05-20

Applicant: Shu-Jen Han ,  Joseph Shu-Tzu Han

Inventor： Shu-Jen Han ,  Joseph Shu-Tzu Han

IPC: G01N27/00

CPC classification number: G01R33/093 ,  B82Y25/00 ,  G01R33/1269

Abstract: The present invention provides a biochip detection device and a detection method thereof. The detection device includes a detection circuit and a biochip containing a plurality of sensor modules. Each sensor modules includes a plurality of giant magnetoresistive biosensors. The detection circuit is arranged to have an end of each biosensor and an end of each of reference sensors respectively connected to first and second voltage sources, whereby current variation induced in each biosensor can be added together. The detection method includes the steps of providing the above described biochip; carrying out surface functionalization on the biosensors; spotting surfaces of the biosensors with probe molecules corresponding to target molecules to complete molecule immobilization; applying a purified sample to the biochip so that target molecules existing in the sample bind to the probe molecules on the surfaces of the biosensors; applying detecting molecules that are combined with magnetic nano-particles to the biochip in such a way that the detecting molecules are complementary to and thus bound to the target molecules; and using the above mentioned detection circuit to supply an output of a detection current of the biosensors so that observation of variation thereof is made to determine existence of the target molecules.

Abstract translation: 本发明提供一种生物芯片检测装置及其检测方法。 检测装置包括检测电路和包含多个传感器模块的生物芯片。 每个传感器模块包括多个巨磁阻生物传感器。 检测电路设置成具有每个生物传感器的端部，并且每个参考传感器的端部分别连接到第一和第二电压源，由此可以将每个生物传感器中引起的电流变化加在一起。 检测方法包括提供上述生物芯片的步骤; 在生物传感器上进行表面官能化; 用对应于靶分子的探针分子发射生物传感器的表面以完成分子固定化; 将纯化的样品施加到生物芯片上，使得存在于样品中的靶分子与生物传感器表面上的探针分子结合; 将与磁性纳米颗粒结合的检测分子施加到生物芯片上，使得检测分子与靶分子互补并因此结合到靶分子; 并且使用上述检测电路来提供生物传感器的检测电流的输出，使得观察其变化来确定目标分子的存在。

公开(公告)号：US10101299B2

公开(公告)日：2018-10-16

申请号：US13046368

申请日：2011-03-11

Applicant: Shan X. Wang ,  Richard S. Gaster ,  Liang Xu ,  Shu-Jen Han ,  Robert Wilson

Inventor： Shan X. Wang ,  Richard S. Gaster ,  Liang Xu ,  Shu-Jen Han ,  Robert Wilson

IPC: G01N27/00 ,  G01N27/74 ,  G01N33/557

Abstract: Methods for quantitatively determining a binding kinetic parameter of a molecular binding interaction are provided. Aspects of embodiments of the methods include: producing a magnetic sensor device including a magnetic sensor in contact with an assay mixture including a magnetically labeled molecule to produce a detectable molecular binding interaction; obtaining a real-time signal from the magnetic sensor; and quantitatively determining a binding kinetics parameter of the molecular binding interaction from the real-time signal. Also provided are systems and kits configured for use in the methods.

公开(公告)号：US08828824B2

公开(公告)日：2014-09-09

申请号：US13074878

申请日：2011-03-29

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

IPC: H01L21/336

CPC classification number: H01L29/7781 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置在可以包括III-V半导体表面层（例如砷化镓（GaAs））和掩埋层（例如AlAs）的分层半导体晶片上限定FET基座。 介电材料，例如氧化铝（AlO），至少在FET源极/漏极区域中围绕基座。 导电盖帽在相对的通道端部封闭通道侧壁。 绝缘体上的III-V（IIIVOI）器件形成电介质材料层的厚度超过器件长度的一半。 源极/漏极触点形成到盖并终止在掩埋层中的介电材料之中/之上。

公开(公告)号：US08786018B2

公开(公告)日：2014-07-22

申请号：US13610158

申请日：2012-09-11

Applicant: Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

Inventor： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78678 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0516 ,  Y10S977/742

Abstract: Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

Abstract translation: 提供了使用选择性电介质沉积技术形成的自对准碳纳米结构场效应晶体管结构。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。

公开(公告)号：US08742475B2

公开(公告)日：2014-06-03

申请号：US13554294

申请日：2012-07-20

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

IPC: H01L21/02

CPC classification number: H01L29/42368 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66477

Abstract: In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.

Abstract translation: 在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层 第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

公开(公告)号：US20140073093A1

公开(公告)日：2014-03-13

申请号：US13610991

申请日：2012-09-12

Applicant: Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

Inventor： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L21/336

CPC classification number: H01L29/78669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78678 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0516 ,  Y10S977/742

Abstract: Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

Abstract translation: 提供了自对准碳纳米结构场效应晶体管结构，其使用选择性电介质沉积技术发泡。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。