公开(公告)号：US20060134912A1

公开(公告)日：2006-06-22

申请号：US11298978

申请日：2005-12-09

申请人： Ravi Iyer ,  Sujit Sharan

发明人： Ravi Iyer ,  Sujit Sharan

IPC分类号： H01L21/44

CPC分类号： C23C16/08 ,  H01L21/28556 ,  H01L21/28568 ,  Y10S438/909

摘要： A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.

摘要翻译： 公开了一种通过化学气相沉积沉积钛金属层的工艺。 该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。

公开(公告)号：US06974726B2

公开(公告)日：2005-12-13

申请号：US10748446

申请日：2003-12-30

申请人： Ashay A. Dani ,  Gudbjorg H. Oskarsdottir ,  Chris Matayabas, Jr. ,  Sujit Sharan ,  Chris L. Rumer ,  Beverly J. Canham

发明人： Ashay A. Dani ,  Gudbjorg H. Oskarsdottir ,  Chris Matayabas, Jr. ,  Sujit Sharan ,  Chris L. Rumer ,  Beverly J. Canham

IPC分类号： H01L21/44 ,  H01L21/78 ,  H01L23/544

CPC分类号： H01L21/78 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/00

摘要： A silicon wafer has a plurality of integrated circuits terminated on a surface of the silicon wafer. The silicon wafer has a soluble protective coat on the surface of the silicon wafer. The coated silicon wafer may be processed by laser scribing. A solvent wash may be used to remove the soluble protective coat and debris from laser scribing. The coated silicon wafer may be saw cut after laser scribing. A flow of solvent may be provided during the saw cutting. The flow of solvent may be sufficient to remove at least a substantial portion of the soluble protective coat.

摘要翻译： 硅晶片具有端接在硅晶片表面上的多个集成电路。 硅晶片在硅晶片的表面上具有可溶的保护涂层。 涂覆的硅晶片可以通过激光划线来加工。 可以使用溶剂洗涤剂从激光划线中除去可溶性保护涂层和碎屑。 涂覆的硅晶片可以在激光划线之后锯切。 在锯切期间可以提供溶剂流。 溶剂的流动可能足以除去至少大部分的可溶性保护涂层。

公开(公告)号：US06943107B2

公开(公告)日：2005-09-13

申请号：US10915935

申请日：2004-08-10

申请人： Gurtej S. Sandhu ,  Sujit Sharan

发明人： Gurtej S. Sandhu ,  Sujit Sharan

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/02667 ,  C30B1/02 ,  C30B29/34 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/32053 ,  H01L29/7842

摘要： A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

摘要翻译： 形成结晶相材料的方法包括：a）在第一结晶相的结晶材料内部或在其中邻近的第一结晶相中提供应力诱导材料; 和b）在有效地将其转变成第二结晶相的条件下退火第一结晶相的结晶材料。 应力诱导材料优选在与第二结晶相退火期间在第一结晶相内诱导压应力，以降低所需的活化能以产生更致密的第二结晶相。 示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而用于提供层的应力诱导材料是Ge，W和Co 在压应力诱导材料设置在其上提供结晶相材料的晶片的相同侧上时，其被设置为具有小于第一相结晶材料的热膨胀系数。 在压应力诱导材料设置在提供结晶相材料的晶片的相对侧上的情况下，其被设置为具有大于第一相结晶材料的热膨胀系数。 具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSi x x。

公开(公告)号：US06908849B2

公开(公告)日：2005-06-21

申请号：US10931854

申请日：2004-09-01

申请人： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

发明人： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC分类号： H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/45

CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868 ,  H01L21/76877 ,  H01L29/456

摘要： A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

摘要翻译： 形成在硅衬底的接合区域上的高纵横比接触结构包括散布有硅化钛层的钛，其沉积在接触开口中并直接接触衬底的上表面。 在沉积期间从SiH 4 Si的添加中CVD钛的掺杂减少了在随后的硅化反应期间底物硅的消耗，其中钛与硅反应形成提供低电阻的硅化钛层 接合区域和硅衬底之间的电接触。 接触结构还包括氮化钛接触填料，其沉积在接触开口中并基本上填充整个接触开口。

公开(公告)号：US06773502B2

公开(公告)日：2004-08-10

申请号：US10300482

申请日：2002-11-19

申请人： Gurtej S. Sandhu ,  Sujit Sharan

发明人： Gurtej S. Sandhu ,  Sujit Sharan

IPC分类号： C30B2502

CPC分类号： H01L21/02667 ,  C30B1/02 ,  C30B29/34 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/32053 ,  H01L29/7842

摘要： Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

摘要翻译： 形成导电线的方法包括在与第一结晶相的结晶材料可操作地相邻处提供应力诱导材料或压应力诱导层。 此外，这些方法包括在有效地将其转变为第二结晶相的条件下退火第一结晶相的结晶材料。 一些方法还包括将应力诱导材料提供到难熔金属层中。 示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而示例的应力诱导材料包括Ge，W和Co。当压应力诱导材料设置在提供结晶相材料的晶片的同一侧时， 具有小于第一相结晶材料的热膨胀系数。 具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSix。

公开(公告)号：US06737328B1

公开(公告)日：2004-05-18

申请号：US09497080

申请日：2000-02-02

申请人： Sujit Sharan ,  Gurtej S. Sandhu

发明人： Sujit Sharan ,  Gurtej S. Sandhu

IPC分类号： H01L2120

CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76224

摘要： In one aspect, the invention includes a method of forming a, silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an, etch rate; a ratio of the deposition rate to the etch rate being at least: about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. In yet another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) not cooling the substrate with a coolant gas while depositing the silicon dioxide.

摘要翻译： 一方面，本发明包括形成二氧化硅层的方法，包括：a）在基底附近形成高密度等离子体，所述等离子体包括二氧化硅前体; b）从前体形成二氧化硅，二氧化硅以沉积速率沉积在衬底上; 和c）在沉积时，以蚀刻速率用等离子体蚀刻沉积的二氧化硅; 沉积速率与蚀刻速率的比率为至少约4:1。 另一方面，本发明包括形成二氧化硅层的方法，包括：a）在基底附近形成高密度等离子体; b）将气体流入等离子体，至少一些形成二氧化硅的气体; c）将由气体形成的二氧化硅沉积在衬底上; 和d）同时沉积二氧化硅，保持基板的温度大于或等于约500℃。另一方面，本发明包括形成二氧化硅层的方法，包括：a）形成高的 靠近基底的密度等离子体; b）将气体流入等离子体，至少一些形成二氧化硅的气体; c）将由气体形成的二氧化硅沉积在衬底上; 和d）在沉积二氧化硅的同时不用冷却剂气体冷却衬底。

公开(公告)号：US06554910B1

公开(公告)日：2003-04-29

申请号：US08649262

申请日：1996-05-17

申请人： Gurtej S. Sandhu ,  Sujit Sharan

发明人： Gurtej S. Sandhu ,  Sujit Sharan

IPC分类号： B08B704

CPC分类号： C23C16/4407 ,  B08B7/00 ,  B08B7/0035 ,  C23C16/4404

摘要： Metal-based residues in semiconductor processing chambers are treated using treatment gases to neutralize and/or facilitate removal of the residues. The treatment gases may neutralize reactive residues by conversion to essentially stable materials. The treatment gases may facilitate removal of residues by converting the residues to materials that are not strongly bound to semiconductor processing chamber surfaces.

摘要翻译： 使用处理气体处理半导体处理室中的金属残留物以中和和/或促进残余物的去除。 处理气体可以通过转化为基本上稳定的材料来中和反应残余物。 处理气体可以通过将残留物转化为不牢固地结合到半导体处理室表面的材料来促进残留物的去除。

公开(公告)号：US06388284B2

公开(公告)日：2002-05-14

申请号：US09754924

申请日：2001-01-03

申请人： Howard E. Rhodes ,  Lyle D. Breiner ,  Philip J. Ireland ,  Trung Tri Doan ,  Gurtej S. Sandhu ,  Sujit Sharan

发明人： Howard E. Rhodes ,  Lyle D. Breiner ,  Philip J. Ireland ,  Trung Tri Doan ,  Gurtej S. Sandhu ,  Sujit Sharan

IPC分类号： H01L27108

CPC分类号： H01L28/84 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/87 ,  H01L28/91 ,  H01L29/94

摘要： Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.

摘要翻译： 描述了集成电路电容器及其形成方法。 根据一个实施方式，形成电容器板，并在其上形成导电层材料。 优选地，材料的导电层比形成电容器板的材料更具导电性。 在优选的实施方案中，材料的导电层包括含钛或钛的层。 在另一优选实施方式中，电容器板包括具有大致粗糙化表面积的外表面的内电容器板。 在该实施方式的一个方面，粗糙化的表面积包括半球形晶粒多晶硅。 根据本发明形成的电容器特别适用于动态随机存取存储器（DRAM）电路。

公开(公告)号：US06335282B1

公开(公告)日：2002-01-01

申请号：US09383888

申请日：1999-08-26

申请人： Sujit Sharan ,  Gurtej S. Sandhu

发明人： Sujit Sharan ,  Gurtej S. Sandhu

IPC分类号： H01L2144

CPC分类号： H01L21/28568 ,  H01L21/28518

摘要： The invention includes methods of forming titanium comprising layers, and methods of forming conductive silicide contacts. In one implementation, a method of forming a titanium comprising layer includes chemical vapor depositing a layer a majority of which comprises elemental titanium, titanium silicide or a mixture thereof over a substrate using a precursor gas chemistry comprising titanium and chlorine. The layer comprises chlorine from the precursor gas chemistry. The layer is exposed to a hydrogen containing plasma effective to drive chlorine from the layer. In one implementation, a method of forming a conductive silicide contact includes forming an insulating material over a silicon comprising substrate. An opening is formed into the insulating material over a node location on the silicon comprising substrate to which electrical connection is desired. A layer is chemical vapor deposited over the substrate using a precursor gas chemistry comprising titanium and chlorine. The layer comprises chlorine from the precursor gas chemistry. The depositing forms a majority of the layer over the node location as titanium silicide, and a majority of the layer over the insulating material as elemental titanium. At least the majority titanium silicide portion of the layer is exposed to a hydrogen containing plasma effective to drive chlorine therefrom.

摘要翻译： 本发明包括形成包含层的钛的方法以及形成导电硅化物接触的方法。 在一个实施方案中，形成包含钛的层的方法包括化学气相沉积层，其中大部分包括元素钛，硅化钛或其混合物，使用包含钛和氯的前体气体化学物质在衬底上。 该层包括来自前体气体化学物质的氯。 该层暴露于含氢等离子体中，有效地驱使层中的氯。 在一个实施方案中，形成导电硅化物接触的方法包括在包含硅的衬底上形成绝缘材料。 在需要电连接的硅包含衬底上的节点位置上形成绝缘材料的开口。 使用包含钛和氯的前体气体化学，在衬底上化学气相沉积一层。 该层包括来自前体气体化学物质的氯。 沉积形成作为硅化钛的节点位置上的层的大部分，绝缘材料上的绝大多数层作为元素钛。 至少该层的多数硅化钛部分暴露于含氢等离子体中，从而驱动氯。

公开(公告)号：US06258724B1

公开(公告)日：2001-07-10

申请号：US09541160

申请日：2000-03-31

申请人： Sujit Sharan

发明人： Sujit Sharan

IPC分类号： H01L21302

CPC分类号： H01L21/76801 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/7682 ,  H01L2221/1047 ,  Y10S977/712 ,  Y10S977/78 ,  Y10S977/831 ,  Y10S977/891

摘要： A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.

摘要翻译： 提供了低介电常数材料和用于可控地降低这种材料层的介电常数的方法，并且包括以下步骤：在足以使氧气的温度和压力下将电介质材料层暴露于氧等离子体的浓度 等离子体以蚀刻介电材料层以在介电材料层中形成空隙。 该方法还可以包括通过控制空隙的尺寸和密度来控制介电常数的降低的步骤。 空隙的大小和密度可以通过改变反应发生的压力，通过改变反应的温度，通过改变反应中使用的氧等离子体的浓度或通过改变反应的组合来控制 这些参数。 本发明的方法在半导体器件的制造中特别有用。