公开(公告)号：US5589413A

公开(公告)日：1996-12-31

申请号：US562868

申请日：1995-11-27

申请人： Hung-Cheng Sung ,  Ling Chen

发明人： Hung-Cheng Sung ,  Ling Chen

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An EPROM device is provided with self-aligned bit-lines. A tunnel oxide layer is formed on a semiconductor substrate. Blanket layers of doped, polysilicon layer, an interelectrode dielectric layer and a blanket polycide layer are formed over the dielectric layer. A TEOS dielectric layer is formed over the blanket polycide layer and a silicon nitride layer. A self-aligned source and drain etching process forms EPROM gate electrode stacks with trench spaces between the stacks in an array. Source/drain dopant ions are implanted in an MDD N+ process between the stacks forming alternating source and drain regions below the spaces between the sidewalls. Spacer dielectric structures are formed adjacent to the sidewalls over the drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filling the spaces over the source regions. An additional N+ implant is made between the spacers into the drain regions. A blanket BPTEOS dielectric layer is formed over the stacks, spaces and sidewalls. Drain bit-line openings are etched to the drain regions through the blanket dielectric layer and the tunnel oxide layer over the drain regions between the spacers. A barrier metal layer of titanium/titanium nitride is formed over the drain regions. A conductive metal layer in contact with the drain regions through the bit-line openings is etched to form the metal layer leaving the bit-lines across the device and contacting with the drain regions.

摘要翻译： EPROM器件具有自对准位线。 隧道氧化物层形成在半导体衬底上。 在电介质层上形成掺杂多晶硅层，电极间电介质层和覆盖多晶硅化物层的覆盖层。 在覆盖的多晶硅化物层和氮化硅层上形成TEOS电介质层。 自对准源极和漏极蚀刻工艺形成具有阵列中的堆叠之间的沟槽空间的EPROM栅电极堆叠。 源/漏掺杂剂离子注入在MDD N +工艺之间，在堆叠之间形成在侧壁之间的空间之下的交替的源极和漏极区域。 间隔电介质结构形成在漏区附近的侧壁附近，留下狭窄的漏极间隔，间隔绝缘塞完全填充源区上的空间。 在隔离件之间形成另外的N +注入到漏区。 在堆叠，空间和侧壁上形成覆盖的BPTEOS电介质层。 排水位线开口通过覆盖层介电层和间隔物之间​​的漏极区上的隧道氧化物层蚀刻到漏极区。 在漏极区域上形成钛/氮化钛的阻挡金属层。 蚀刻通过位线开口与漏极区域接触的导电金属层，以形成跨越器件的位线并与漏极区域接触的金属层。

公开(公告)号：US08610220B2

公开(公告)日：2013-12-17

申请号：US13472890

申请日：2012-05-16

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US08384149B2

公开(公告)日：2013-02-26

申请号：US11785608

申请日：2007-04-19

申请人： Shih Wei Wang ,  Te-Hsun Hsu ,  Hung-Cheng Sung

发明人： Shih Wei Wang ,  Te-Hsun Hsu ,  Hung-Cheng Sung

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L29/42336

摘要： A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells.

摘要翻译： 半导体存储器件包括衬底和形成在衬底中的沟槽。 每个与对应的第一和第二存储器单元相关联的第一和第二浮动栅极延伸到沟槽中。 由于可以使沟槽相对较深，所以可以使浮动栅极相对较大，同时浮动栅极的横向尺寸保持较小。 此外，尽管存储单元的横向范围减小，浮栅和形成沟道区的沟槽的侧壁之间的绝缘体厚度可以做得相对较厚。 编程门延伸到第一和第二浮栅之间的沟槽中，并且与源区域一起被两个存储单元共享。

公开(公告)号：US07880217B2

公开(公告)日：2011-02-01

申请号：US11192669

申请日：2005-07-30

申请人： Hung-Cheng Sung ,  Te-Hsun Hsu ,  Shih-Wei Wang

发明人： Hung-Cheng Sung ,  Te-Hsun Hsu ,  Shih-Wei Wang

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/66825

摘要： A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric disposed over the floating gate electrode; and, a control gate damascene electrode extending through a dielectric insulating layer in electrical communication with the inter-gate dielectric, the control gate damascene electrode disposed over an upper portion of the floating gate electrode.

摘要翻译： 一种可编程非易失性存储器（PNVM）器件和形成与CMOS逻辑器件工艺兼容的方法，以改善工艺流程，PNVM器件包括半导体衬底有源区; 有源区上的栅极电介质; 栅极电介质上的浮栅电极; 设置在所述浮栅上的栅极间电介质; 以及延伸穿过与所述栅极间电介质电连通的介电绝缘层的控制栅极镶嵌电极，所述控制栅极镶嵌电极设置在所述浮栅电极的上部。

公开(公告)号：US07608884B2

公开(公告)日：2009-10-27

申请号：US11088492

申请日：2005-03-24

申请人： Te-Hsun Hsu ,  Hung-Cheng Sung

发明人： Te-Hsun Hsu ,  Hung-Cheng Sung

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.

摘要翻译： 系统和方法提供了闪存中改进的源耦合比。 在一个实施例中，具有高源耦合比率的快闪存储器单元系统至少包括具有浮置栅极，漏极和源极的常规浮动栅极器件。 浮置栅极形成在第一结上，用于通过从源极到浮置栅极的电子注入来对浮置栅极充电，并且至少第一电介质层叠在浮置栅极的顶部上以形成第二结。 至少第一多晶硅层叠在第一电介质的顶部上，第一多晶硅电连接到源极。 通过第二结提供到浮栅的电子隧穿对浮置栅极充电，从而增加浮栅的源极耦合比并提高存储电荷的效率。

公开(公告)号：US20060214214A1

公开(公告)日：2006-09-28

申请号：US11088492

申请日：2005-03-24

申请人： Te-Hsun Hsu ,  Hung-Cheng Sung

发明人： Te-Hsun Hsu ,  Hung-Cheng Sung

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.

摘要翻译： 系统和方法提供了闪存中改进的源耦合比。 在一个实施例中，具有高源耦合比率的快闪存储器单元系统至少包括具有浮置栅极，漏极和源极的常规浮动栅极器件。 浮置栅极形成在第一结上，用于通过从源极到浮置栅极的电子注入来对浮置栅极充电，并且至少第一电介质层叠在浮置栅极的顶部上以形成第二结。 至少第一多晶硅层叠在第一电介质的顶部上，第一多晶硅电连接到源极。 通过第二结提供到浮栅的电子隧穿对浮置栅极充电，从而增加浮栅的源极耦合比并提高存储电荷的效率。

公开(公告)号：US20050239247A1

公开(公告)日：2005-10-27

申请号：US10833179

申请日：2004-04-27

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Te-Hsun Hsu

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Te-Hsun Hsu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L23/544 ,  H01L27/115

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L22/34 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

摘要翻译： 实现了在制造存储器件中形成浮栅隔离测试结构的新方法。 该方法包括提供基底。 栅极氧化层形成在衬底上。 沉积栅极氧化物层的浮栅导体层。 图案化浮栅导体层以暴露用于计划源区的衬底。 将离子注入到暴露的基底中以形成源区。 接触结构形成于源区。 接触结构形成于浮栅导体层。

公开(公告)号：US06872667B1

公开(公告)日：2005-03-29

申请号：US10721979

申请日：2003-11-25

申请人： Chang-Jen Shieh ,  Hung-Cheng Sung

发明人： Chang-Jen Shieh ,  Hung-Cheng Sung

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L21/31116 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/11534

摘要： Methods of fabricating semiconductor devices using separate periphery and cell region etching steps are provided. A substrate is provided, wherein the substrate has a cell region and a periphery region separated by a shallow trench isolation (STI). The STI is filled with a dielectric material. A protective layer is formed on the periphery region, allowing semiconductor structures to be formed in the cell region without damaging the surface of the periphery region. Upon forming the semiconductor structures in the cell region, a portion of the dielectric material in the STI adjacent to the cell region is partially removed. The dielectric material adjacent to the periphery region is substantially unetched.

摘要翻译： 提供了使用分离的周边和单元区域蚀刻步骤制造半导体器件的方法。 提供了一种衬底，其中衬底具有由浅沟槽隔离（STI）隔开的单元区域和外围区域。 STI填充有电介质材料。 在周边区域形成有保护层，能够在电池区域内形成半导体结构体而不会损伤周边区域的表面。 在单元区域中形成半导体结构时，部分去除与单元区域相邻的STI中的电介质材料的一部分。 邻近周边区域的电介质材料基本上未被蚀刻。

公开(公告)号：US07056791B2

公开(公告)日：2006-06-06

申请号：US10859125

申请日：2004-06-03

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang ,  Hsui Ouyang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang ,  Hsui Ouyang

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  Y10S438/981

摘要： A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.

摘要翻译： 一种制造嵌入式闪存器件的方法。 提供具有存储区域的衬底。 在存储区域中的衬底上形成器件。 导电层形成在衬底上以覆盖存储区域中的器件。 在导电层和基板上形成保形绝缘层。 绝缘层在存储区域的边缘被去除。 通过各向异性蚀刻，去除绝缘层和导电层的一部分以在器件的侧壁上形成控制栅极。 因此，不会发生由常规控制栅极处理引起的多晶硅残渣。

公开(公告)号：US20050258467A1

公开(公告)日：2005-11-24

申请号：US10851841

申请日：2004-05-21

申请人： Shih-Wei Wang ,  Hung-Cheng Sung

发明人： Shih-Wei Wang ,  Hung-Cheng Sung

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/76

CPC分类号： B82Y10/00 ,  H01L29/40114 ,  H01L29/42332

摘要： A non-volatile memory device and a method for fabricating the non-volatile memory device employ at least one charge storage dot formed upon a substrate. At least one of an oxidation inhibiting layer and a charge storage enhancing layer is formed upon the charge storage dot. A silicon nitride material layer may simultaneously provide oxidation inhibiting properties and charge storage enhancing properties. The non-volatile memory device is formed with enhanced performance.

摘要翻译： 非易失性存储器件和用于制造非易失性存储器件的方法使用形成在衬底上的至少一个电荷存储点。 在电荷存储点上形成氧化抑制层和电荷存储增强层中的至少一种。 氮化硅材料层可以同时提供氧化抑制性质和电荷存储增强性能。 非易失性存储器件具有增强的性能。