公开(公告)号：US06825114B1

公开(公告)日：2004-11-30

申请号：US10424675

申请日：2003-04-28

申请人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

摘要翻译： 使用非晶碳掩模形成用于集成电路的熔丝的方法包括在导电层上提供包含无定形碳的掩模材料层。 掩模材料层掺杂有氮，并且在掩模层上形成抗反射涂层（ARC）特征。 根据ARC特征去除掩模材料层的一部分以形成掩模，并且去除ARC特征以形成翘曲的掩模。 根据翘曲的掩模对导电层进行图案化，去除翘曲的掩模，并且在图案化的导电层上提供硅化物层。

公开(公告)号：US06627360B1

公开(公告)日：2003-09-30

申请号：US09900985

申请日：2001-07-09

申请人： Scott A. Bell ,  Christopher F. Lyons

发明人： Scott A. Bell ,  Christopher F. Lyons

IPC分类号： G03F900

CPC分类号： H01L21/32139 ,  G03F7/40 ,  G03F7/405 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31155

摘要： A method of forming an etch mask includes patterning a top surface of a photoresist layer, carbonizing the patterned top surface of the photoresist layer and selectively removing portions of the photoresist layer. Portions of the photoresist layer under the carbonized areas remain. A substrate or a layer above substrate can be etched or processed in accordance with the mask formed from the photoresist layer.

摘要翻译： 形成蚀刻掩模的方法包括图案化光致抗蚀剂层的顶表面，碳化光致抗蚀剂层的图案化顶表面并选择性地去除光致抗蚀剂层的部分。 在碳化区域下方的光致抗蚀剂层的部分保留。 可以根据由光致抗蚀剂层形成的掩模来蚀刻或处理衬底或衬底上的层。

公开(公告)号：US06544885B1

公开(公告)日：2003-04-08

申请号：US09706498

申请日：2000-11-03

申请人： Khanh B. Nguyen ,  Harry J. Levinson ,  Christopher F. Lyons ,  Scott A. Bell ,  Fei Wang ,  Chih Yuh Yang

发明人： Khanh B. Nguyen ,  Harry J. Levinson ,  Christopher F. Lyons ,  Scott A. Bell ,  Fei Wang ,  Chih Yuh Yang

IPC分类号： H01L2358

CPC分类号： H01L21/76895 ,  H01L21/32139 ,  H01L2924/0002 ,  Y10S438/95 ,  H01L2924/00

摘要： A method of forming a conductor pattern on a base with uneven topography includes placing conductor material on the base, placing a hard mask material on the conductor material, planarizing an exposed surface of the hard mask material, and placing a layer of resist on the hard mask material. The resist is patterned and the patterned resist is used in selectively etching the hard mask material, with the hard mask material used in selectively etching the underlying conductor material. By planarizing the hard mask material prior to placing a layer of resist thereupon, uniformity of the resist coating is enhanced and depth of focus problems in exposing the resist are reduced.

摘要翻译： 在具有不平坦的地形的基底上形成导体图案的方法包括将导体材料放置在基底上，将硬掩模材料放置在导体材料上，平坦化硬掩模材料的暴露表面，以及将一层抗蚀剂放置在硬 面具材料。 抗蚀剂被图案化，并且图案化的抗蚀剂用于选择性地蚀刻硬掩模材料，其中硬掩模材料用于选择性蚀刻下面的导体材料。 通过在放置一层抗蚀剂之前对硬掩模材料进行平面化，抗蚀剂涂层的均匀性得到提高，并且降低了曝光抗蚀剂的焦点深度问题。

公开(公告)号：US06380047B1

公开(公告)日：2002-04-30

申请号：US09634990

申请日：2000-08-08

申请人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.

摘要翻译： 使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料 沟渠 然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。 由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。 此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。

公开(公告)号：US06306560B1

公开(公告)日：2001-10-23

申请号：US09204630

申请日：1998-12-02

申请人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

发明人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

IPC分类号： G03C500

CPC分类号： H01L21/31144 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/32139

摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon oxynitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon oxynitride layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon oxynitride layer; etching the exposed portion of the silicon oxynitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

摘要翻译： 在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：在氧化物层上方提供包括金属层，金属层上的氧化物层和氧氮化硅层的半导体衬底; 在所述氮氧化硅层上沉积超薄光致抗蚀剂，所述超薄光致抗蚀剂具有小于约的厚度; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 显影暴露一部分氮氧化硅层的超薄光刻胶; 蚀刻暴露氧化物层的一部分的氧氮化硅层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

公开(公告)号：US06183938B2

公开(公告)日：2001-02-06

申请号：US09207551

申请日：1998-12-08

申请人： Christopher F. Lyons ,  Michael K. Templeton

发明人： Christopher F. Lyons ,  Michael K. Templeton

IPC分类号： G03F700

CPC分类号： H01L21/3088 ,  G03F7/00 ,  G03F7/0035 ,  G03F7/0045 ,  H01L21/0338

摘要： In one embodiment, the present invention relates to a method of making a sub-lithographic structure involving the steps of providing a nitrogen rich film over a portion of a substrate; depositing a photoresist over the nitrogen rich film and the substrate, wherein the photoresist and the nitrogen rich film interact and form a thin desensitized resist layer around an interface between the photoresist and the nitrogen rich film; exposing the photoresist to radiation; developing the photoresist exposing the thin desensitized resist layer; directionally etching a portion of the thin desensitized resist layer; and removing the nitrogen rich film leaving the sub-lithographic structure on the substrate.

摘要翻译： 在一个实施方案中，本发明涉及一种制备亚光刻结构的方法，其涉及以下步骤：在衬底的一部分上提供富氮膜; 在富氮膜和衬底上沉积光致抗蚀剂，其中光致抗蚀剂和富氮膜相互作用并在光致抗蚀剂和富氮膜之间的界面周围形成薄的脱敏抗蚀剂层; 将光致抗蚀剂暴露于辐射; 显影曝光薄的脱敏抗蚀剂层的光致抗蚀剂; 定向蚀刻一部分薄的脱敏抗蚀剂层; 并除去留在基板上的亚光刻结构的富氮膜。

公开(公告)号：US6162587A

公开(公告)日：2000-12-19

申请号：US203450

申请日：1998-12-01

申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  G03C5/00

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

公开(公告)号：US6140023A

公开(公告)日：2000-10-31

申请号：US203447

申请日：1998-12-01

申请人： Harry J. Levinson ,  Scott A. Bell ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

发明人： Harry J. Levinson ,  Scott A. Bell ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

IPC分类号： G03F7/075 ,  G03F7/40 ,  G03F9/00

CPC分类号： G03F7/405 ,  G03F7/075 ,  G03F7/40

摘要： A lithographic process for fabricating sub-micron features is provided. A silicon containing ultra-thin photoresist is formed on an underlayer surface to be etched. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern. The ultra-thin photoresist is oxidized so as to convert the silicon therein to silicon dioxide. The oxidized ultra-thin photoresist layer is used as a hard mask during an etch step to transfer the pattern to the underlayer. The etch step includes an etch chemistry that is highly selective to the underlayer over the oxidized ultra-thin photoresist layer.

摘要翻译： 提供了用于制造亚微米特征的光刻工艺。 在要蚀刻的底层表面上形成含硅的超薄光致抗蚀剂。 用短波长辐射图案化超薄光致抗蚀剂层以限定图案。 超薄光致抗蚀剂被氧化以将其中的硅转化为二氧化硅。 氧化的超薄光致抗蚀剂层在蚀刻步骤期间用作硬掩模以将图案转印到底层。 蚀刻步骤包括对氧化的超薄光致抗蚀剂层上的底层具有高选择性的蚀刻化学品。

公开(公告)号：US6127070A

公开(公告)日：2000-10-03

申请号：US203283

申请日：1998-12-01

申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0274 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a nitride layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the nitride layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer and the dielectric layer. The nitride layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在电介质层上形成氮化物层。 在氮化物层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行图案化，以形成通孔图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转移到氮化物层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的氮化物层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，氮化物层用作硬掩模，以通过蚀刻介电层的部分来形成与通孔图案相对应的接触孔。

公开(公告)号：US6124183A

公开(公告)日：2000-09-26

申请号：US992490

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.

摘要翻译： 使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分 绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。 由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。