公开(公告)号：US5870046A

公开(公告)日：1999-02-09

申请号：US837702

申请日：1997-04-22

Applicant: Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

Inventor： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC: H04B14/06 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06 ,  H03M3/02

CPC classification number: H04B14/062 ,  H04L25/0266 ,  H04L25/06 ,  H04M11/06 ,  H04L7/033

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

公开(公告)号：US5583706A

公开(公告)日：1996-12-10

申请号：US341723

申请日：1994-11-17

Applicant: Trent O. Dudley ,  William G. Gliss ,  Richard T. Behems ,  David R. Welland

Inventor： Trent O. Dudley ,  William G. Gliss ,  Richard T. Behems ,  David R. Welland

IPC: G11B19/04 ,  G11B20/10 ,  G11B20/14 ,  G11B5/09

CPC classification number: G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1403 ,  G11B19/04

Abstract: In a sampled amplitude read channel for magnetic recording, a nonlinear discrete time decimation filter in a negative feed back loop adjusts a DC offset in an analog read signal from a magnetic read head without distorting the read signal. In sampled amplitude recording, adding the samples of an isolated positive pulse to the samples of an isolated negative pulse generates the DC offset of the discrete time sample values. A decimation filter adds the sample values from a positive pulse to the sample values of a negative pulse in order to detect and pass the DC offset in the read signal. The detected discrete time DC offset from the discrete time decimation filter is converted into an analog DC offset signal and subtracted from the analog read signal in a negative feedback loop. A running average decimation filter removes the DC offset during acquisition, and a decision-directed decimation filter removes the DC offset during tracking.

Abstract translation: 在用于磁记录的采样幅度读取通道中，负反馈回路中的非线性离散时间抽取滤波器调整来自磁读头的模拟读取信号中的DC偏移，而不会使读取信号失真。 在采样振幅记录中，将隔离的正脉冲的样本加到分离的负脉冲的采样中，产生离散时间采样值的直流偏移。 抽取滤波器将来自正脉冲的采样值与负脉冲的采样值相加，以便检测并通过读信号中的直流偏移。 从离散时间抽取滤波器检测到的离散时间直流偏移被转换为模拟直流偏移信号，并从负反馈回路中的模拟读取信号中减去。 运行平均抽取滤波器在采集期间去除DC偏移，并且决策导频抽取滤波器在跟踪期间去除DC偏移。

公开(公告)号：US4709225A

公开(公告)日：1987-11-24

申请号：US809530

申请日：1985-12-16

Applicant: David R. Welland ,  Michael J. Callahan

Inventor： David R. Welland ,  Michael J. Callahan

IPC: H01L27/04 ,  G01R17/02 ,  G01R27/26 ,  H01L21/822 ,  H03M1/10 ,  H03M1/38 ,  H03M1/46 ,  H03M1/80

CPC classification number: H03M1/1061 ,  G01R17/02 ,  G01R27/2605 ,  H03M1/468 ,  H03M1/804

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted. In another aspect of the invention, capacitance-adjustment steps are sequentially interleaved with analog-to-digital conversions in an analog-to-digital converter.

Abstract translation: 一种用于调整单片集成电路中的电容的方法，其中期望电容形成二进制加权序列的顺序包括与主电容器并联的修整电容器顺序连接，并且当连接每个修整电容器时，确定所得的并行 电容大于或小于参考电容的电容。 如果结果电容太大，则修剪电容器断开，否则将被连接。 重复该过程，直到尝试了每个微调电容器。 为了调整下一个最大电容的电容，最后得到的电容与参考电容并联连接以形成新的参考电容。 然后用下一个最大的初级电容器重复该过程，直到与每一个初级电容器相关的最终的电容器被调整。 在本发明的另一方面，电容调节步骤在模数转换器中顺序地与模数转换交替。

公开(公告)号：US4471324A

公开(公告)日：1984-09-11

申请号：US340878

申请日：1982-01-19

Applicant: David R. Welland

Inventor： David R. Welland

IPC: H03G3/12 ,  H03G1/00 ,  H03G3/02 ,  H03G3/30 ,  H03G7/00 ,  H03G7/08

CPC classification number: H03G1/0005 ,  H03G7/002

Abstract: A signal gain controlled system comprises an operational amplifier including a feedback path between the input and output terminals of the amplifier. The system includes first variable impedance means for varying the output voltage at the output terminal of the amplifier in response to and as a function of the input current signal applied to the input terminal and a first control signal. A signal path coupled between the output terminal of the operational amplifier and the output terminal of the system includes second variable impedance means for varying the output current of the system in response to and as a function of (a) the output voltage at the output of the amplifier and (b) a second control signal. The signal gain of the system is a function of the ratio of the second and first control signals.The preferred amplifier is the type having an input resistance and a feedback resistance, wherein at least one of the resistances includes a transistor which is biased to operate in its saturated region. The gain of the amplifier is a function of the control signal applied to the base of the saturated transistor.The signal gain controlled system can be utilized with a level sensing detector to provide signal compression or expansion.

Abstract translation: 信号增益控制系统包括运算放大器，其包括放大器的输入和输出端之间的反馈路径。 该系统包括用于响应于并且作为施加到输入端的输入电流信号和第一控制信号而改变放大器输出端的输出电压的第一可变阻抗装置。 耦合在运算放大器的输出端和系统的输出端之间的信号通路包括第二可变阻抗装置，用于响应于（a）输出端的输出电压而改变系统的输出电流 放大器和（b）第二控制信号。 系统的信号增益是第二和第一控制信号的比率的函数。 优选的放大器是具有输入电阻和反馈电阻的类型，其中至少一个电阻包括被偏置以在其饱和区域中工作的晶体管。 放大器的增益是施加到饱和晶体管基极的控制信号的函数。 信号增益控制系统可以与电平检测检测器一起使用，以提供信号压缩或扩展。

公开(公告)号：US4434380A

公开(公告)日：1984-02-28

申请号：US316754

申请日：1981-10-30

Applicant: David R. Welland

Inventor： David R. Welland

IPC: H03G3/10 ,  H03G1/00 ,  G06G7/26 ,  G06G7/24

CPC classification number: H03G1/0005

Abstract: An improved multiplier circuit of the type including an input operational amplifier and a gain cell is disclosed. The gain cell is connected to the amplifier such that a first signal can be generated in response to and as a logarithmic function of an input signal, a control signal can be added to the first signal and a second signal can be algebraically generated as an antilogarithmic function of the algebraic sum of the first and control signals. The improvement includes means for providing a correcting signal as a function of the control signal at the output of the input amplifier substantially equal and opposite to signals produced at the output of the input amplifier by changes in the control signal.

Abstract translation: 公开了一种包括输入运算放大器和增益单元的改进的乘法器电路。 增益单元连接到放大器，使得可以响应于输入信号的对数函数和作为输入信号的对数函数产生第一信号，可以将控制信号添加到第一信号，并且可以将代码生成第二信号作为反对数 第一和控制信号的代数和的函数。 该改进包括用于在输入放大器的输出处提供校正信号作为函数的装置，该输入放大器的输出基本上与输入放大器的输出端产生的信号基本上相等并且与控制信号的变化相反。

公开(公告)号：US09250137B2

公开(公告)日：2016-02-02

申请号：US13624619

申请日：2012-09-21

Applicant: David R. Welland

Inventor： David R. Welland

IPC: G01K7/00 ,  G01K7/01

CPC classification number: G01K7/01 ,  G01K7/34 ,  G01K2219/00

Abstract: A method includes alternately coupling a selected one of a plurality of current sources and two or more of the plurality of current sources to a first terminal of a bipolar device during first and second phases of a modulator cycle of a plurality of modulator cycles. The method further includes providing sampled voltages from the first terminal of the bipolar device to a modulator to produce a modulator output signal, filtering the modulator output signal to produce a filtered output signal using a back-end filter having an impulse response, and determining a temperature in response to the filtered output signal.

Abstract translation: 一种方法包括在多个调制器周期的调制器周期的第一和第二阶段期间交替地将多个电流源中的一个电流源和两个或更多个多个电流源交替耦合到双极器件的第一端子。 该方法还包括将采样的电压从双极器件的第一端子提供给调制器以产生调制器输出信号，使用具有脉冲响应的后端滤波器对调制器输出信号进行滤波以产生滤波后的输出信号，并且确定 响应于滤波的输出信号的温度。

公开(公告)号：US07804364B2

公开(公告)日：2010-09-28

申请号：US11022560

申请日：2004-12-22

Applicant: Timothy J. Dupuis ,  David R. Welland ,  Susanne A. Paul ,  Ali M. Niknejad

Inventor： Timothy J. Dupuis ,  David R. Welland ,  Susanne A. Paul ,  Ali M. Niknejad

IPC: H03F3/04

CPC classification number: H03F3/2173 ,  H01L23/645 ,  H01L2223/6644 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H03F3/195 ,  H03F3/2176 ,  H03F3/30 ,  H03F3/72 ,  H03K17/04163 ,  H03K17/6872 ,  H01L2224/0401

Abstract: A method and apparatus is provided for detecting the output power of a power amplifier. The output power is detected by detecting the absolute values of the voltage and current at the output of the amplifier and mixing the detected voltage and current to generate a signal related to the output power.

Abstract translation: 提供了一种用于检测功率放大器的输出功率的方法和装置。 通过检测放大器输出端的电压和电流的绝对值来检测输出功率，并混合检测的电压和电流以产生与输出功率有关的信号。

公开(公告)号：US07203224B2

公开(公告)日：2007-04-10

申请号：US10601411

申请日：2003-06-23

Applicant: Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

Inventor： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC: H04B1/38

CPC classification number: H04L25/0266 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

Abstract translation: 提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。 本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。 该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。 可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。 隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。 最后，提供双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。 在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。

公开(公告)号：US07200167B2

公开(公告)日：2007-04-03

申请号：US10127285

申请日：2002-04-22

Applicant: Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

Inventor： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC: H04B1/38 ,  H04L5/16

CPC classification number: H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M1/76 ,  H04M3/007 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

Abstract translation: 提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。 本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。 该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。 可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。 隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。 最后，提供双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。 在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。

公开(公告)号：US07046793B2

公开(公告)日：2006-05-16

申请号：US10879956

申请日：2004-06-29

Applicant: George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

Inventor： George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC: H04M1/00 ,  H04M9/00

CPC classification number: H04L25/0266 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06 ,  H04M19/001

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines. Briefly described, a means for providing a proper hookswitch transition for a variety of international phone standards is provided. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DAA circuitry may be utilized which satisfies many or all hookswitch transition standards without the use of additional discrete devices. The hookswitch transition standards may be satisfied by ramping down the current flowing through the hookswitch prior to transitioning the hookswitch state. In this manner the hookswitch current change as a function of time (di/dt) may be decreased. Thus, the current through the hookswitch may be actively controlled prior to switching the hookswitch from an off-hook condition to an on-hook condition. By controlling the current drawn from the phone lines through the hookswitch, the maximum voltage seen at the phone company exchange may be decreased.

Abstract translation: 可以使用数字直接访问布置（DAA）电路来终止用户端的电话连接，以提供用于到达和来自电话线的信号的通信路径。 简而言之，提供了一种用于为各种国际电话标准提供适当的钩开关转换的装置。 本发明还可以用于在电容隔离屏障上传输和接收信号的装置。 更具体地，可以使用满足许多或所有钩开关转换标准的DAA电路，而不使用额外的分立器件。 钩子开关转换标准可以通过在转换钩形开关状态之前降低流过钩形开关的电流来实现。 以这种方式，作为时间（di / dt）的函数的钩开关电流变化可能会减小。 因此，在将钩形开关从摘机状态切换到挂机状态之前，可以主动地控制通过钩形开关的电流。 通过控制通过钩形开关从电话线吸取的电流，电话公司交换所看到的最大电压可能会降低。