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103 条记录 (耗时 0.037 秒)

    Flexible RAM Clock Enable
    92.
    发明申请
    Flexible RAM Clock Enable 有权
    灵活的RAM时钟使能

    公开(公告)号：US20080253220A1

    公开(公告)日：2008-10-16

    申请号：US12145440

    申请日：2008-06-24

    申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    IPC分类号： G11C8/18

    CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

    摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

    摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

    Versatile logic element and logic array block
    93.
    发明授权
    Versatile logic element and logic array block 有权

    公开(公告)号：US07432734B2

    公开(公告)日：2008-10-07

    申请号：US11743625

    申请日：2007-05-02

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

    Automatic adjustment of optimization effort in configuring programmable devices
    94.
    发明授权
    Automatic adjustment of optimization effort in configuring programmable devices 有权
    自动调整配置可编程设备的优化工作

    公开(公告)号：US07415682B2

    公开(公告)日：2008-08-19

    申请号：US11097592

    申请日：2005-04-01

    申请人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    发明人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    IPC分类号： G06F17/50 ,  H03K17/693

    CPC分类号： G06F17/5054

    摘要： User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.

    摘要翻译： 用户设计被分配到与用户设计相关联的每个设计目标的类别。 每个类别代表满足设计目标的难度。 优化阶段根据类别的不同组合进行调整，并根据分配给用户设计的类别进行选择。 根据与用户设计相关的类别确定设计目标相对难度的排名。 优化阶段的参数可以根据这个排名进行修改，将优化工作集中在具体的设计目标上。 参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。 如果优化阶段的结果不满足设计目标，则可以将用户设计重新分类为另外的类别，并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。

    Distributed random access memory in a programmable logic device
    96.
    发明授权
    Distributed random access memory in a programmable logic device 有权
    可编程逻辑器件中的分布式随机存取存储器

    公开(公告)号：US07304499B1

    公开(公告)日：2007-12-04

    申请号：US11454815

    申请日：2006-06-16

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17736

    摘要： Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.

    摘要翻译： 可编程逻辑器件中的分布式随机存取存储器使用配置RAM位作为分布式RAM的位。 单个写入路径用于提供配置数据和用户写入数据。 选择电路，例如多路复用器，用于确定单个写入路径是否携带配置数据或用户写入数据。 在本发明的另一方面，配置RAM位用于构造移位寄存器，通过添加传输晶体管将配置RAM位链连接在一起，并且以彼此相位180°异相的两个时钟计​​时交替传输晶体管。

    VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK
    97.
    发明申请
    VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK 有权

    公开(公告)号：US20070252617A1

    公开(公告)日：2007-11-01

    申请号：US11743625

    申请日：2007-05-02

    申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

    Distributed memory in field-programmable gate array integrated circuit devices
    98.
    发明申请
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US20070146178A1

    公开(公告)日：2007-06-28

    申请号：US11320253

    申请日：2005-12-27

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Wong ,  Andy Lee ,  Philip Pan

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Wong ,  Andy Lee ,  Philip Pan

    IPC分类号： H03M7/00

    CPC分类号： G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    摘要翻译： 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。