公开(公告)号：US20080265426A1

公开(公告)日：2008-10-30

申请号：US11943820

申请日：2007-11-21

申请人： Robert Seidel ,  Ralf Richter ,  Frank Feustel

发明人： Robert Seidel ,  Ralf Richter ,  Frank Feustel

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76885

摘要： A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process.

摘要翻译： 一种形成半导体结构的方法包括提供包括第一材料层的衬底。 在第一材料层上形成保护层。 在第一材料层和保护层中形成至少一个开口。 在第一材料层上形成第二材料层，并且保护层用第二材料填充开口。 执行平面化处理以去除开口外部的第二材料层的部分。 在平坦化处理期间，保护层的至少一部分不被去除。 执行蚀刻处理以去除在平坦化处理期间未被去除的保护层的部分。

公开(公告)号：US07306976B2

公开(公告)日：2007-12-11

申请号：US11284292

申请日：2005-11-21

申请人： Frank Feustel ,  Matthias Lehr ,  Frank Kuechenmeister

发明人： Frank Feustel ,  Matthias Lehr ,  Frank Kuechenmeister

IPC分类号： H01L21/48

CPC分类号： H01L23/295 ,  H01L21/563 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： During the formation of an underfill material provided between a carrier substrate and a semiconductor chip, a common motion of particles contained in the underfill material is initiated towards the semiconductor chip, thereby adjusting the thermal and mechanical behavior of the underfill material. For instance, by applying an external force, such as gravity, a depletion zone with respect to the filler particles may be created in the vicinity of the carrier substrate, while a high particle concentration may be obtained in the vicinity of the semiconductor chip. Hence, thermal and mechanical stress redistribution by means of the underfill material may be enhanced.

摘要翻译： 在载体基板和半导体芯片之间形成的底部填充材料的形成期间，向底部填充材料中包含的颗粒的共同运动开始朝向半导体芯片，由此调整底部填充材料的热和机械性能。 例如，通过施加诸如重力的外力，可能在载体基板附近产生相对于填料颗粒的耗尽区，而在半导体芯片附近可以获得高的颗粒浓度。 因此，可以增强借助于底部填充材料的热和机械应力再分配。

公开(公告)号：US20050242435A1

公开(公告)日：2005-11-03

申请号：US11046986

申请日：2005-01-31

申请人： James Werking ,  Frank Feustel ,  Christian Zistl ,  Peter Huebler

发明人： James Werking ,  Frank Feustel ,  Christian Zistl ,  Peter Huebler

IPC分类号： H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/48 ,  H01L23/50 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.

摘要翻译： 将诸如二氧化硅或氟掺杂二氧化硅的增强的机械稳定性的介电材料引入到低k互连结构的通孔水平中，特别是在器件的封装期间提供了更高的总体机械稳定性。 因此，即使使用有机封装基板，在高端低k互连结构中经常观察到的裂纹和分层也可能显着降低。

公开(公告)号：US08399335B2

公开(公告)日：2013-03-19

申请号：US12970117

申请日：2010-12-16

申请人： Torsten Huisinga ,  Michael Grillberger ,  Frank Feustel

发明人： Torsten Huisinga ,  Michael Grillberger ,  Frank Feustel

IPC分类号： H01L21/76

CPC分类号： H01L23/53238 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/53252 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In sophisticated semiconductor devices, densely packed metal line layers may be formed on the basis of an ultra low-k dielectric material, wherein corresponding modified portions of increased dielectric constant may be removed in the presence of the metal lines, for instance, by means of a selective wet chemical etch process. Consequently, the metal lines may be provided with desired critical dimensions without having to take into consideration a change of the critical dimensions upon removing the modified material portion, as is the case in conventional strategies.

摘要翻译： 在复杂的半导体器件中，可以在超低k介电材料的基础上形成密集的金属线层，其中可以在金属线的存在下去除相对于介电常数增加的改性部分，例如通过 选择性湿化学蚀刻工艺。 因此，如在常规策略中的情况那样，金属线可以设置有所需的临界尺寸，而不必考虑去除改性材料部分时临界尺寸的变化。

公开(公告)号：US08153524B2

公开(公告)日：2012-04-10

申请号：US12711373

申请日：2010-02-24

申请人： Oliver Aubel ,  Joerg Hohage ,  Frank Feustel ,  Axel Preusse

发明人： Oliver Aubel ,  Joerg Hohage ,  Frank Feustel ,  Axel Preusse

IPC分类号： H01L21/44

CPC分类号： H01L21/76826 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76864 ,  Y10S438/906

摘要： During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.

摘要翻译： 在形成复杂的金属化系统期间，可以在含铜金属区域上形成导电覆盖层，以增强电迁移行为，而不会不利地影响总导电性。 同时，可以进行热化学处理以提供敏感电介质材料的优异的表面条件并且还抑制碳消耗，这常常导致敏感的ULK材料的材料特性的显着变化。

公开(公告)号：US07915170B2

公开(公告)日：2011-03-29

申请号：US11625579

申请日：2007-01-22

申请人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

发明人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

IPC分类号： H01L21/311

CPC分类号： H01L21/76801 ,  H01L21/02087 ,  H01L21/3043 ,  H01L21/31144 ,  H01L21/76802

摘要： By providing a protection layer at the bevel region, the deposition of polymer materials during the patterning process of complex metallization structures may be reduced. Additionally or alternatively, a surface topography may be provided, for instance in the form of respective recesses, in order to enhance the degree of adhesion of any materials deposited in the bevel region during the manufacturing of complex metallization structures. Advantageously, the provision of the protection layer providing the reduced polymer deposition may be combined with the modified surface topography.

摘要翻译： 通过在斜面区域设置保护层，可以减少复杂金属化结构的图形化过程期间聚合物材料的沉积。 附加地或替代地，可以提供例如各自凹部的形式的表面形貌，以便在复杂金属化结构的制造期间增强沉积在斜面区域中的任何材料的粘附程度。 有利的是，提供提供降低的聚合物沉积的保护层可以与改性表面形貌组合。

公开(公告)号：US20110049727A1

公开(公告)日：2011-03-03

申请号：US12854441

申请日：2010-08-11

申请人： Oliver Aubel ,  Frank Feustel ,  Christian Hennesthal

发明人： Oliver Aubel ,  Frank Feustel ,  Christian Hennesthal

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/02074 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a complex metallization system, the probability of dielectric breakdown may be reduced by vertically separating a critical area of high electric field strength and an area of reduced dielectric strength of the interlayer dielectric material. For this purpose, the interlayer dielectric material may be recessed after forming the metal regions and/or the metal regions may be increased in height and the corresponding recess may be refilled with an appropriate dielectric material.

摘要翻译： 在复杂的金属化系统中，可以通过垂直分离高电场强度的关键区域和层间介电材料的降低的介电强度的面积来降低电介质击穿的可能性。 为此，层间介电材料可以在形成金属区域之后凹陷，和/或金属区域的高度可以增加，并且相应的凹部可以用合适的介电材料重新填充。

公开(公告)号：US20100221911A1

公开(公告)日：2010-09-02

申请号：US12711373

申请日：2010-02-24

申请人： Oliver Aubel ,  Joerg Hohage ,  Frank Feustel ,  Axel Preusse

发明人： Oliver Aubel ,  Joerg Hohage ,  Frank Feustel ,  Axel Preusse

IPC分类号： H01L21/768

CPC分类号： H01L21/76826 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76864 ,  Y10S438/906

摘要： During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.

摘要翻译： 在形成复杂的金属化系统期间，可以在含铜金属区域上形成导电覆盖层，以增强电迁移行为，而不会不利地影响总导电性。 同时，可以进行热化学处理以提供敏感电介质材料的优异的表面条件并且还抑制碳消耗，这常常导致敏感的ULK材料的材料特性的显着变化。

公开(公告)号：US20090181537A1

公开(公告)日：2009-07-16

申请号：US12411873

申请日：2009-03-26

申请人： ROBERT SEIDEL ,  Ralf Richter ,  Frank Feustel

发明人： ROBERT SEIDEL ,  Ralf Richter ,  Frank Feustel

IPC分类号： H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76885

摘要： A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process.

摘要翻译： 一种形成半导体结构的方法包括提供包括第一材料层的衬底。 在第一材料层上形成保护层。 在第一材料层和保护层中形成至少一个开口。 在第一材料层上形成第二材料层，并且保护层用第二材料填充开口。 执行平面化处理以去除开口外部的第二材料层的部分。 在平坦化处理期间，保护层的至少一部分不被去除。 执行蚀刻处理以去除在平坦化处理期间未被去除的保护层的部分。

公开(公告)号：US20080206994A1

公开(公告)日：2008-08-28

申请号：US11866701

申请日：2007-10-03

申请人： Frank Feustel ,  Robert Seidel ,  Juergen Boemmels

发明人： Frank Feustel ,  Robert Seidel ,  Juergen Boemmels

IPC分类号： H01L21/302

CPC分类号： H01L21/3212

摘要： Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may be polished with a high removal rate due to the mechanical and the chemical action of the slurry material, while the chemical interaction with the slurry material may be substantially avoided in areas of reduced height level. Therefore, a high process uniformity may be achieved even for pronounced initial surface topographies and slurry materials having a component of high chemical reactivity.

摘要翻译： 在执行用于平坦化先进半导体器件的金属化水平的CMP工艺之前，可以形成适当的盖层，以便将高度水平降低的金属区域暴露于高度化学反应性浆料材料。 因此，由于浆料的机械和化学作用，可以以高的去除速度抛光增加的高度水平的金属，同时可以在降低高度水平的区域中基本避免与浆料的化学相互作用。 因此，即使对于具有高化学反应性的组分的显着的初始表面形貌和浆料材料也可以获得高的工艺均匀性。