公开(公告)号：US06800898B2

公开(公告)日：2004-10-05

申请号：US09951239

申请日：2001-09-12

申请人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

发明人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

IPC分类号： H01L2976

CPC分类号： H01L27/10844 ,  H01L27/10861 ,  H01L27/10876

摘要： The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.

摘要翻译： 形成在基板中的凹部的下部的底部和侧面具有绝缘结构。 第一导电类型的导电结构的第一部分位于凹部的下部。 低于第一类型的第二导电类型的导电结构的第二部分位于上部并且在凹部的侧面与基板的区域相邻。 导电结构在其第一和第二部分之间具有扩散阻挡层。 导电结构被配置为具有垂直晶体管的DRAM单元配置的位线，由此S / Du表示下源极/漏极区域，S / Do表示连接到存储电容器的上部源极/漏极区域。 或者，导电结构被配置为存储电容器，并且上部源极漏极/区域连接到位线。

公开(公告)号：US06674132B2

公开(公告)日：2004-01-06

申请号：US09927554

申请日：2001-08-09

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L2994

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11519

摘要： A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region formed in a semiconductor body. The gate electrode is a component of a strip-shaped word line. Source and drain regions are disposed between gate electrodes of adjacent memory cells. Source regions are provided with polysilicon layers, in the form of a strip, as common source lines. Drain regions are connected as bit lines through polysilicon fillings to metallic interconnects applied to the top face of the semiconductor body.

摘要翻译： 通过STI沟槽与其他存储单元隔离的存储单元各自包括在栅电极和形成在半导体本体中的沟道区之间的ONO层结构。 栅电极是条形字线的分量。 源区和漏区设置在相邻存储单元的栅电极之间。 源区域设置有作为公共源极线的条带形式的多晶硅层。 漏极区域通过多晶硅填充物作为位线连接到施加到半导体主体的顶面的金属互连。

公开(公告)号：US06627498B2

公开(公告)日：2003-09-30

申请号：US10093722

申请日：2002-03-08

申请人： Josef Willer ,  Veronika Polei

发明人： Josef Willer ,  Veronika Polei

IPC分类号： H01L218247

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged thereon. The storage layer is replaced above the channel region by an etching layer made of Al2O3. During fabrication, the etching layer is etched out laterally and the second boundary layer is thus undercut. The resulting interspaces are filled with the material of the storage layer. The provision of suitable spacers makes it possible to define the dimensions of the memory cell.

摘要翻译： 存储单元在半导体材料中具有源极区域和漏极区域，并且在源极和漏极区域之间的沟道区域之上，具有在边界层之间的存储层和布置在其上的栅电极的三层层结构。 通过由Al 2 O 3制成的蚀刻层在沟道区域之上替换存储层。 在制造过程中，蚀刻层被横向蚀刻，因此第二边界层被切割。 所产生的间隙填充有存储层的材料。 提供合适的间隔物使得可以限定存储单元的尺寸。

公开(公告)号：US06608340B1

公开(公告)日：2003-08-19

申请号：US09821853

申请日：2001-03-30

申请人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L2972

CPC分类号： H01L27/10864

摘要： A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.

摘要翻译： 凹陷从基板的主表面延伸到所述基板的内部，并且具有上部区域和相邻的下部区域。 平行于主表面的上部区域的横截面设置有至少一个角部。 平行于主表面的下部区域的横截面与上部区域的横截面特别是在上部区域附近匹配，具有以下差异：每个角都是圆形的，由此下部区域的横截面 面积小于上部区域的横截面。 为了产生凹陷，上部区域设置有通过各向同性蚀刻而被圆化的辅助间隔件。 通过选择性地蚀刻基板以形成辅助间隔物来产生下部区域。

公开(公告)号：US06599797B1

公开(公告)日：2003-07-29

申请号：US09980811

申请日：2002-03-11

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10888 ,  H01L27/1203

摘要： The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z). A conducting structure (L) is located in the dent and adjoins the silicon layer (S) and the silicon substrate (1) so that the channel zone of the MOS transistors is electrically connected to the silicon substrate.

摘要翻译： 本发明涉及一种SOI衬底，其具有穿过硅层和SiO 2层（O）的凹部。 位于硅层（S）的范围内的所述凹部（V）的上部具有水平的第一横截面的圆筒形状。 与凹部（V）的上部相比，位于SiO 2层（O）的范围内的凹部（V）的下部被凸出到具有水平的圆筒形状的程度 第二横截面大于第一横截面。 在凹部（V）中设置绝缘材料的圆筒（Z）。 所述气缸的水平截面对应于第一横截面，其下部位于凹部（V）的下部。 凹陷横向围绕气缸（Z）的下部。 导电结构（L）位于凹陷中并与硅层（S）和硅衬底（1）相邻，使得MOS晶体管的沟道区电连接到硅衬底。

公开(公告)号：US06583632B2

公开(公告)日：2003-06-24

申请号：US09767392

申请日：2001-01-23

申请人： Paul-Werner Von Basse ,  Josef Willer

发明人： Paul-Werner Von Basse ,  Josef Willer

IPC分类号： G01R2726

CPC分类号： G06K9/0002 ,  G01R27/2605

摘要： A grid of capacitor surfaces is connected to read lines and control lines. The read lines are connected alternately to the output of a feedback operational amplifier and to a collecting capacitor. The capacitances to be measured are charged repeatedly and the charges are collected on the collecting capacitors. Between the charging operations, the potential on the read lines is kept constant through the use of the low-resistance output of the operational amplifier. The use of this method in the case of a fingerprint sensor makes it possible to evaluate all the read lines together.

摘要翻译： 电容器表面的栅格连接到读取线和控制线。 读取线交替地连接到反馈运算放大器的输出端和集电电容器。 要测量的电容重复充电，并将电荷收集在收集电容器上。 在充电操作之间，通过使用运算放大器的低电阻输出，读取线路上的电位保持不变。 在指纹传感器的情况下使用该方法可以将所有的读取行一起评估。

公开(公告)号：US06518613B2

公开(公告)日：2003-02-11

申请号：US09968304

申请日：2001-10-01

申请人： Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

发明人： Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

摘要： A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.

摘要翻译： 存储单元的MOS晶体管和与其连接的位线设置在基板的第一表面上。 存储单元的电容器设置在基板的第二表面上，第二表面与第一表面相对。 接触件设置在衬底中并将电容器连接到MOS晶体管。

公开(公告)号：US06309930B1

公开(公告)日：2001-10-30

申请号：US09708636

申请日：2000-11-09

申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

IPC分类号： H01L21336

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.

摘要翻译： SRAM单元布置包括每个存储单元的六个MOS晶体管，其被形成为垂直晶体管。 MOS晶体管布置在沟槽（G1，G2，G4）的侧壁处。 诸如例如形成隔离物的栅极（Ga2，Ga4）或导电结构（L3）的存储单元的部分通过布置在衬底的表面（O）上方的相邻的水平导电结构（H5）接触 S）。 存储器单元的部分之间的连接经由经由扩散区（D2）布置在凹陷和字线（W）的侧壁处的第三导电结构（L3），其经由衬底（S）内的凹陷的侧壁相邻的经由 通过相对于垂直于表面（O）的轴线以不同高度部分布置的第二位线（B2）或/和经由导电结构（L1，L2，L6）的第一位线。 触点（K5）同时接触MOS晶体管的多个部分。

公开(公告)号：US6125050A

公开(公告)日：2000-09-26

申请号：US335365

申请日：1999-06-17

申请人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul-Werner Basse ,  Wolfgang Krautschneider

发明人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul-Werner Basse ,  Wolfgang Krautschneider

IPC分类号： H01L27/112 ,  G11C5/02 ,  H01L21/8246

CPC分类号： H01L27/0207 ,  H01L27/1126 ,  H01L27/11293 ,  H01L27/11803

摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.

摘要翻译： 平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。 多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。 每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。

公开(公告)号：US5500385A

公开(公告)日：1996-03-19

申请号：US451534

申请日：1995-05-26

申请人： Hermann Wendt ,  Josef Willer ,  Hans Reisinger ,  Volker Lehmann

发明人： Hermann Wendt ,  Josef Willer ,  Hans Reisinger ,  Volker Lehmann

IPC分类号： H01L27/04 ,  H01L21/225 ,  H01L21/334 ,  H01L21/822 ,  H01L21/762

CPC分类号： H01L29/66181 ,  Y10S438/924 ,  Y10S438/928 ,  Y10S438/977

摘要： For manufacturing a silicon capacitor, hole openings are produced in an n-doped silicon substrate, a p.sup.+ -doped region is formed at the surface thereof and this surface is provided with a dielectric layer together with a conductive layer. The silicon substrate is thinned with an etching proceeding from the back side, this etching attacking silicon selectively to p.sup.+ -doped silicon and therefore stopping when the p.sup.+ -doped region is reached.

摘要翻译： 为了制造硅电容器，在n掺杂硅衬底中产生孔开口，在其表面形成p +掺杂区域，并且该表面与导电层一起设置介电层。 硅衬底通过从背面进行的蚀刻变薄，该蚀刻选择性地攻击到p +掺杂的硅，因此当达到p +掺杂区域时停止。