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172 条记录 (耗时 0.025 秒)

    Method for capacitive image acquisition
    2.
    发明授权
    Method for capacitive image acquisition 失效
    电容式图像采集方法

    公开(公告)号：US06365888B2

    公开(公告)日：2002-04-02

    申请号：US09782733

    申请日：2001-02-13

    申请人： Paul-Werner Von Basse ,  Josef Willer ,  Thomas Scheiter ,  Stephan Marksteiner

    发明人： Paul-Werner Von Basse ,  Josef Willer ,  Thomas Scheiter ,  Stephan Marksteiner

    IPC分类号： H01L2700

    CPC分类号： G06K9/0002

    摘要： A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.

    摘要翻译： 导体区域的格子阵列用于电容图像采集。 每个壳体中的屏蔽导体都设置在用于测量的导体之间。 在多个充电和放电循环期间，为了防止屏蔽电容器之间的位移电流，电势总是沿着属于相应像素的导体承载。 作为示例，具有反馈运算放大器的补偿线可以用于相同地改变导体上的电位。

    SRAM cell arrangement and method for manufacturing same
    3.
    发明授权
    SRAM cell arrangement and method for manufacturing same 有权
    SRAM单元布置及其制造方法

    公开(公告)号：US06222753B1

    公开(公告)日：2001-04-24

    申请号：US09446419

    申请日：1999-12-20

    申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    IPC分类号： G11C700

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

    摘要翻译： 每个存储单元包括六个MOS晶体管的SRAM单元布置，其中每个晶体管形成为垂直晶体管。 MOS晶体管布置在沟槽的侧壁。 存储单元的部分，例如栅极电极或形成为间隔物的导电结构，经由布置在衬底表面上方的相邻的水平导电结构接触。 存储器单元的部分之间的连接通过布置在凹陷和字线的侧壁处的第三导电结构经由第一位线经由第二位线和/或通孔的扩散区域经由衬底内的凹陷的侧壁相邻布置 相对于垂直于表面的轴部分地布置在不同高度的导电结构。 触头同时接触MOS晶体管的多个部分。

    Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials
    4.
    发明授权
    Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials 失效
    半导体元件具有由两种不同介电材料的钝化层形成的双钝化层

    公开(公告)号：US06664612B2

    公开(公告)日：2003-12-16

    申请号：US09757328

    申请日：2001-01-09

    申请人： Josef Willer ,  Paul-Werner Von Basse ,  Thomas Scheiter

    发明人： Josef Willer ,  Paul-Werner Von Basse ,  Thomas Scheiter

    IPC分类号： H01L2358

    CPC分类号： G06K9/0002 ,  H01L21/3145

    摘要： A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.

    摘要翻译： 具有钝化的半导体部件包括至少两个双钝化层，其中最上层被施加到位于其下方的层的平坦表面。 双钝化层包括两层不同的介电材料，例如氧化硅和氮化硅。 单个钝化层的各自的厚度可以适应于施加钝化层的层的结构尺寸。 这产生了可靠的钝化，其特别适用于电容测量指纹传感器。

    Method for the manufacturing a memory cell configuration
    5.
    发明授权
    Method for the manufacturing a memory cell configuration 失效
    制造存储单元配置的方法

    公开(公告)号：US6153475A

    公开(公告)日：2000-11-28

    申请号：US331495

    申请日：1999-06-21

    申请人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Wolfgang Krautschneider ,  Paul-Werner von Basse

    发明人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Wolfgang Krautschneider ,  Paul-Werner von Basse

    IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/336

    CPC分类号： H01L27/112

    摘要： For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.

    摘要翻译： PCT No.PCT / DE97 / 02549 Sec。 371 1999年6月21日第 102（e）日期1999年6月21日PCT 1997年11月4日PCT PCT。 第WO98 / 27586号公报 日期1998年6月25日为了制造具有包括垂直MOS晶体管的第一存储单元和不包括MOS晶体管的第二存储单元的存储单元布置，由此存储单元沿带状沟槽的相对边缘布置 沿着沟槽（5）相邻的存储单元依次制造。 特别是通过间隔物技术来确定相邻存储单元的间隔。 通过这种方式，可以实现1F2的每个存储单元的空间要求，由此F是相应技术的最小结构尺寸。

    Method of determining very small capacitances
    6.
    发明授权
    Method of determining very small capacitances 失效
    确定极小电容的方法

    公开(公告)号：US06583632B2

    公开(公告)日：2003-06-24

    申请号：US09767392

    申请日：2001-01-23

    申请人： Paul-Werner Von Basse ,  Josef Willer

    发明人： Paul-Werner Von Basse ,  Josef Willer

    IPC分类号： G01R2726

    CPC分类号： G06K9/0002 ,  G01R27/2605

    摘要： A grid of capacitor surfaces is connected to read lines and control lines. The read lines are connected alternately to the output of a feedback operational amplifier and to a collecting capacitor. The capacitances to be measured are charged repeatedly and the charges are collected on the collecting capacitors. Between the charging operations, the potential on the read lines is kept constant through the use of the low-resistance output of the operational amplifier. The use of this method in the case of a fingerprint sensor makes it possible to evaluate all the read lines together.

    摘要翻译： 电容器表面的栅格连接到读取线和控制线。 读取线交替地连接到反馈运算放大器的输出端和集电电容器。 要测量的电容重复充电，并将电荷收集在收集电容器上。 在充电操作之间，通过使用运算放大器的低电阻输出，读取线路上的电位保持不变。 在指纹传感器的情况下使用该方法可以将所有的读取行一起评估。

    SRAM cell arrangement and method for manufacturing same
    7.
    发明授权
    SRAM cell arrangement and method for manufacturing same 有权
    SRAM单元布置及其制造方法

    公开(公告)号：US06309930B1

    公开(公告)日：2001-10-30

    申请号：US09708636

    申请日：2000-11-09

    申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    IPC分类号： H01L21336

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.

    摘要翻译： SRAM单元布置包括每个存储单元的六个MOS晶体管，其被形成为垂直晶体管。 MOS晶体管布置在沟槽（G1，G2，G4）的侧壁处。 诸如例如形成隔离物的栅极（Ga2，Ga4）或导电结构（L3）的存储单元的部分通过布置在衬底的表面（O）上方的相邻的水平导电结构（H5）接触 S）。 存储器单元的部分之间的连接经由经由扩散区（D2）布置在凹陷和字线（W）的侧壁处的第三导电结构（L3），其经由衬底（S）内的凹陷的侧壁相邻的经由 通过相对于垂直于表面（O）的轴线以不同高度部分布置的第二位线（B2）或/和经由导电结构（L1，L2，L6）的第一位线。 触点（K5）同时接触MOS晶体管的多个部分。