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    DRAM memory cell for DRAM memory device and method for manufacturing it
    1.
    发明授权
    DRAM memory cell for DRAM memory device and method for manufacturing it 有权
    用于DRAM存储器件的DRAM存储单元及其制造方法

    公开(公告)号：US06566182B2

    公开(公告)日：2003-05-20

    申请号：US09875803

    申请日：2001-06-06

    申请人： Franz Hofmann ,  Till Schlosser

    发明人： Franz Hofmann ,  Till Schlosser

    IPC分类号： H01L218238

    CPC分类号： H01L27/10858 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/1203

    摘要： A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which is capable of being actuated by a control gate electrode extends in a vertical direction between the drain and source regions. A capacitor is stacked under the selection transistor and electrically connected to the source region in the semiconductor substrate column. Above the selection transistor is a metal bit line electrically connected to the drain region in the semiconductor substrate column. A metal word line in direct electrical communication with the control gate electrode of the selection transistor extends perpendicularly with respect to the metal bit line.

    摘要翻译： DRAM存储单元包括在半导体衬底列中具有漏极区域和源极区域的MOSFET选择晶体管。 能够由控制栅极电极驱动的电流通道在漏极和源极区域之间沿垂直方向延伸。 电容器层叠在选择晶体管的下方并与半导体衬底列中的源极区域电连接。 在选择晶体管上方是与半导体衬底列中的漏极区域电连接的金属位线。 与选择晶体管的控制栅电极直接电连通的金属字线相对于金属位线垂直地延伸。

    Process for producing a web of a semiconductor material
    2.
    发明申请
    Process for producing a web of a semiconductor material 审中-公开
    用于制造半导体材料的网的方法

    公开(公告)号：US20050287772A1

    公开(公告)日：2005-12-29

    申请号：US11145174

    申请日：2005-06-06

    申请人： Till Schlosser ,  Joachim Nutzel

    发明人： Till Schlosser ,  Joachim Nutzel

    IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L29/786 ,  H01L31/20

    CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/78645

    摘要： Process for producing a web of a semiconductor material The invention relates to a process for producing two webs of a semiconductor material, in which a sacrificial web of a first material is produced on a semiconductor substrate, in which the first material is selected in such a way that the crystal structure of the semiconductor substrate is substantially transferred to the sacrificial web, in which the two webs of a semiconductor material are deposited on two opposite side walls of the sacrificial web, in which the crystal structure of the sacrificial web is substantially transferred to the crystal structure of the webs, and in which the sacrificial webs are then removed.

    摘要翻译： 用于制造半导体材料的网的方法本发明涉及一种用于生产半导体材料的两个幅材的方法，其中在半导体衬底上产生第一材料的牺牲幅材，其中第一材料在这种 半导体衬底的晶体结构基本转移到牺牲幅材的方式，其中半导体材料的两个网状物沉积在牺牲幅材的两个相对的侧壁上，其中牺牲幅材的晶体结构基本上被转移 到网的晶体结构，然后去除牺牲性网。

    DRAM cell arrangement with vertical MOS transistors
    5.
    发明申请
    DRAM cell arrangement with vertical MOS transistors 有权
    具有垂直MOS晶体管的DRAM单元布置

    公开(公告)号：US20050253180A1

    公开(公告)日：2005-11-17

    申请号：US11158439

    申请日：2005-06-22

    申请人： Till Schlosser ,  Brian Lee

    发明人： Till Schlosser ,  Brian Lee

    IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L29/423

    CPC分类号： H01L27/10858 ,  H01L27/10852 ,  H01L27/10876

    摘要： The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

    摘要翻译： 本发明涉及具有垂直MOS晶体管的DRAM单元布置。 沿着存储单元矩阵的一列排列的通道区域是由栅介质层包围的肋的部分。 属于一行的MOS晶体管的栅电极是条状字线的一部分，因此在存储单元矩阵的每个交叉点存在垂直双栅极MOS晶体管，其中形成相关联的字线的栅电极 相关肋骨两侧的沟槽。

    Manufacturing method for an integrated semiconductor structure
    7.
    发明申请
    Manufacturing method for an integrated semiconductor structure 有权
    集成半导体结构的制造方法

    公开(公告)号：US20080102578A1

    公开(公告)日：2008-05-01

    申请号：US11588591

    申请日：2006-10-27

    申请人： Till Schlosser

    发明人： Till Schlosser

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L27/10882 ,  H01L27/10891

    摘要： The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure. The method comprises the steps of: forming a peripheral circuitry in a peripheral device region, said peripheral circuitry comprising a peripheral transistor at least partially formed in said semiconductor substrate and having a first gate dielectric formed in a first high temperature process step; forming a plurality of memory cells in a memory cell region, each of said memory cells comprising an access transistor at least partially formed in a semiconductor substrate and having a second gate dielectric formed in a second high temperature process step and having a metallic gate conductor; wherein said first and second high temperature process steps are performed before a step of forming said metallic gate conductor.

    摘要翻译： 本发明提供了一种用于集成半导体结构和相应的半导体结构的制造方法。 该方法包括以下步骤：在外围设备区域中形成外围电路，所述外围电路包括至少部分地形成在所述半导体衬底中并具有在第一高温工艺步骤中形成的第一栅极电介质的外围晶体管; 在存储单元区域中形成多个存储单元，每个所述存储单元包括至少部分地形成在半导体衬底中并且具有在第二高温工艺步骤中形成并具有金属栅极导体的第二栅极电介质的存取晶体管; 其中所述第一和第二高温工艺步骤在形成所述金属栅极导体的步骤之前进行。

    Fabrication method for a trench capacitor with an insulation collar
    8.
    发明申请
    Fabrication method for a trench capacitor with an insulation collar 审中-公开
    具有绝缘套管的沟槽电容器的制造方法

    公开(公告)号：US20050153507A1

    公开(公告)日：2005-07-14

    申请号：US11013921

    申请日：2004-12-17

    申请人： Thomas Hecht ,  Till Schlosser ,  Michael Sesterhenn

    发明人： Thomas Hecht ,  Till Schlosser ,  Michael Sesterhenn

    IPC分类号： H01L21/265 ,  H01L21/76 ,  H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L21/26586

    摘要： The present invention provides a fabrication method for a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact. After forming and sinking an electrically conductive filling, an insulation collar and, if appropriate, a buried contact that is connected on all sides, the following are effected: providing at least one liner layer in the trench; filling the trench with a filling made of an auxiliary material, which filling is encapsulated by the at least one liner layer in the trench; providing a mask on the filling for defining the structure of the buried contact, the mask having no projections into the trench; removing a part of the filling using the mask; removing an underlying part of the at least one liner layer for uncovering a corresponding part of the insulation collar.

    摘要翻译： 本发明提供了一种用于在衬底中具有绝缘套环的沟槽电容器的制造方法，其通过埋入触点在一侧电连接到衬底。 在形成和下沉导电填料之后，绝缘套环以及如果合适的话，在所有侧面上连接的埋入触头都可以实现：在沟槽中提供至少一个衬垫层; 用由辅助材料制成的填充物填充沟槽，该填充物被沟槽中的至少一个衬垫层封装; 在所述填充物上设置掩模以限定所述埋入接触件的结构，所述掩模没有突起到所述沟槽中; 使用掩模去除一部分填充物; 去除所述至少一个衬垫层的下部部分以露出所述绝缘套环的对应部分。