公开(公告)号：US20230223463A1

公开(公告)日：2023-07-13

申请号：US17574661

申请日：2022-01-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Jeffrey B. Johnson ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06 ,  H01L21/763 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/0642 ,  H01L21/763 ,  H01L29/66242

Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.

公开(公告)号：US11639895B2

公开(公告)日：2023-05-02

申请号：US17195887

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik ,  Yusheng Bian

IPC: G01N21/64 ,  G01N21/85 ,  H01L31/0232 ,  H01L31/12 ,  H01L31/02

Abstract: A “lab on a chip” includes an optofluidic sensor and components to analyze signals from the optofluidic sensor. The optofluidic sensor includes a substrate, a channel at least partially defined by a portion of a layer of first material on the substrate, input and output fluid reservoirs in fluid communication with the channel, at least a first radiation source coupled to the substrate adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent and below the channel.

公开(公告)号：US20230087058A1

公开(公告)日：2023-03-23

申请号：US17549013

申请日：2021-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/732 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

公开(公告)号：US20230062194A1

公开(公告)日：2023-03-02

申请号：US17533882

申请日：2021-11-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Alexander M. Derrickson

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

公开(公告)号：US11569405B2

公开(公告)日：2023-01-31

申请号：US16686973

申请日：2019-11-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L31/103 ,  H01L31/18 ,  H01L31/028

Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

公开(公告)号：US20220223688A1

公开(公告)日：2022-07-14

申请号：US17684498

申请日：2022-03-02

Applicant: GlobalFoundries U.S. INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/08 ,  H01L29/78

Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.

公开(公告)号：US11282883B2

公开(公告)日：2022-03-22

申请号：US16713423

申请日：2019-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik

IPC: H01L31/113 ,  H01L27/146

Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.

公开(公告)号：US11271079B2

公开(公告)日：2022-03-08

申请号：US16743584

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

公开(公告)号：US20210351306A1

公开(公告)日：2021-11-11

申请号：US16868773

申请日：2020-05-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L31/0232 ,  H01L27/144 ,  H01L31/028 ,  H01L31/105 ,  H01L31/18

Abstract: A photodetector includes a photodetecting region in a semiconductor substrate, and a reflector extending at least partially along a sidewall of the photodetecting region in the semiconductor substrate. The reflector includes an air gap defined in the semiconductor substrate. The reflector allows use of thinner germanium for the photodetecting region. The air gap may have a variety of internal features to direct electromagnetic radiation towards the photodetecting region.

公开(公告)号：US11171210B2

公开(公告)日：2021-11-09

申请号：US16804435

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Pekarik ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.