公开(公告)号：US06596648B2

公开(公告)日：2003-07-22

申请号：US10193850

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06524907B2

公开(公告)日：2003-02-25

申请号：US10171369

申请日：2002-06-13

申请人： Kunal R. Parekh ,  Charles H. Dennison ,  Jeffrey W. Honeycutt

发明人： Kunal R. Parekh ,  Charles H. Dennison ,  Jeffrey W. Honeycutt

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/76802 ,  H01L21/76834 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/964

摘要： A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

公开(公告)号：US06458649B1

公开(公告)日：2002-10-01

申请号：US09360349

申请日：1999-07-22

申请人： John K. Zahurak ,  Kunal R. Parekh ,  Mark Fischer

发明人： John K. Zahurak ,  Kunal R. Parekh ,  Mark Fischer

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10814 ,  H01L28/91

摘要： Methods of forming capacitor-over-bit line memory cells are described. In one embodiment, a bit line contact opening is etched through conductive bit line material. In one implementation, a bit line contact opening is etched through a previously-formed bit line. In one implementation, a bit line contact opening is etched after forming a bit line.

摘要翻译： 描述形成电容器对位线存储单元的方法。 在一个实施例中，通过导电位线材料蚀刻位线接触开口。 在一个实现中，通过预先形成的位线蚀刻位线接触开口。 在一种实施方式中，在形成位线之后蚀刻位线接触开口。

公开(公告)号：US06423582B1

公开(公告)日：2002-07-23

申请号：US09257756

申请日：1999-02-25

申请人： Mark Fischer ,  Zhiping Yin ,  Thomas R. Glass ,  Kunal R. Parekh ,  Gurtej Singh Sandhu

发明人： Mark Fischer ,  Zhiping Yin ,  Thomas R. Glass ,  Kunal R. Parekh ,  Gurtej Singh Sandhu

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.

摘要翻译： 本发明涉及一种激光熔丝。 激光熔丝包括包含导热材料的元件。 保险丝还包括吸收元件，该吸收元件包括具有与热传导元件重叠的热或光吸收的可调节容量的材料。 保险丝还包括覆盖并包围导热元件和吸收元件的外绝缘元件。

公开(公告)号：US06329684B1

公开(公告)日：2001-12-11

申请号：US08951855

申请日：1997-10-16

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/84 ,  H01L28/87

摘要： The invention encompasses methods of forming DRAM constructions, methods of forming capacitor constructions, DRAM constructions, and capacitor constructions. The invention includes a method in which a) a first layer is formed over a node location; b) a semiconductive material masking layer is formed over the first layer; c) an opening is formed through the semiconductive material masking layer and the first layer to the node location; d) an upwardly open capacitor storage node layer is formed within the opening; e) a storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and a capacitor plate are formed over the storage node. The invention also includes a capacitor structure comprising: a) an insulative layer over a substrate; b) a polysilicon layer over the insulative layer; c) an opening extending through the polysilicon layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions; d) a spacer over the step; e) a storage node layer over the spacer, polysilicon layer and the node; and f) a dielectric layer and a cell plate layer capacitively coupled to the storage node layer.

摘要翻译： 本发明包括形成DRAM结构的方法，形成电容器结构的方法，DRAM结构和电容器结构。 本发明包括一种方法，其中a）在节点位置上形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过半导体材料掩蔽层和第一层到达节点位置形成开口; d）在开口内形成向上开放的电容器存储节点层; e）从掩蔽层和存储节点层形成存储节点; 以及f）在所述存储节点上形成电容器介电层和电容器板。 本发明还包括电容器结构，包括：a）衬底上的绝缘层; b）绝缘层上的多晶硅层; c）延伸穿过所述多晶硅层和所述绝缘层到达节点的开口，所述开口包括上部和下部，所述上部包括第一最小横截面尺寸，并且所述下部包括第二最小横截面 尺寸比第一最小横截面尺寸窄，该开口还包括在上部和下部的界面处的台阶; d）台阶上的间隔物; e）在所述间隔物，多晶硅层和所述节点之上的存储节点层; 以及f）电容耦合到存储节点层的电介质层和电池板层。

公开(公告)号：US06329267B1

公开(公告)日：2001-12-11

申请号：US09520739

申请日：2000-03-07

申请人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

发明人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

IPC分类号： H01L21762

CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

公开(公告)号：US06284641B1

公开(公告)日：2001-09-04

申请号：US09174300

申请日：1998-10-16

申请人： Kunal R. Parekh

发明人： Kunal R. Parekh

IPC分类号： H01L214763

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76882 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10888

摘要： Disclosed is a method of forming a self-aligned contact to a semiconductor substrate by use of a sacrificial spacer. The sacrificial spacer has the advantage of self aligning metallization to the semiconductive substrate or to a polysilicon plug material without extra photolithography steps as are required in the prior art.

摘要翻译： 公开了通过使用牺牲间隔物形成与半导体衬底的自对准接触的方法。 牺牲间隔物具有如下优点，即在现有技术中需要的不需要额外的光刻步骤的情况下，将金属化自对准至半导体衬底或多晶硅插塞材料。

公开(公告)号：US06238999B1

公开(公告)日：2001-05-29

申请号：US09520288

申请日：2000-03-07

申请人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

发明人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

IPC分类号： H01L21762

CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

摘要翻译： 一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。 另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

公开(公告)号：US06238971B1

公开(公告)日：2001-05-29

申请号：US08798242

申请日：1997-02-11

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L28/84 ,  Y10S438/964

摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node. The invention also includes a DRAM cell comprising: a) a bitline node and a capacitor node electrically connected together through a transistor gate; b) a capacitor electrically connected to the capacitor node, the capacitor comprising; i) a storage node, the storage node in lateral cross-section comprising an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and within laterally opposing cavities beneath the storage node; ii) a dielectric layer against the storage node outer surface and extending within the opposing cavities beneath the storage node; and iii) a cell plate layer against the dielectric layer and extending within the opposing cavities beneath the storage node; and c) a bitline electrically connected to the bitline node.

摘要翻译： 本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。 本发明包括形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。 本发明还包括DRAM单元，其包括：a）通过晶体管栅极电连接在一起的位线节点和电容器节点; b）电连接到所述电容器节点的电容器，所述电容器包括： i）存储节点，所述存储节点在横截面中包括沿着所述存储节点的一对相对的侧表面延伸到所述存储节点的顶部的外表面，以及在所述存储节点下方的横向相对的空腔内; ii）抵靠存储节点外表面并在存储节点下面的相对空腔内延伸的电介质层; 以及iii）抵靠所述电介质层并且在所述存储节点下方的相对空腔内延伸的电池板层; 以及c）与所述位线节点电连接的位线。

公开(公告)号：US06207523B1

公开(公告)日：2001-03-27

申请号：US08887742

申请日：1997-07-03

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。