公开(公告)号：US5694364A

公开(公告)日：1997-12-02

申请号：US779186

申请日：1997-01-06

申请人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C5/147

摘要： In the normal mode, a first voltage-down converter down-converts an external power supply voltage to provide a large, first internal power supply voltage to the peripheral circuitry via a first internal power supply voltage supplying line, and a second voltage-down converter down-converts the external power supply voltage to provide a smaller, second internal power supply voltage to a memory cell array via a second internal power supply voltage supplying line. This allows fast operation and reduction in power consumption. In conducting a burn-in test, an external power supply voltage supplying line is connected to the first and second internal power supply voltage supplying lines. Thus, the first and second internal power supply voltage supplying lines directly receive the external power supply voltage. This allows an effective burn-in test. In a burn-in test, the first and second voltage-down converters are inactivated.

摘要翻译： 在正常模式中，第一降压转换器对外部电源电压进行下变频，以经由第一内部电源电压供应线向外围电路提供大的第一内部电源电压，以及第二降压转换器 降低外部电源电压，以经由第二内部电源电压供给线向存储单元阵列提供较小的第二内部电源电压。 这允许快速操作和降低功耗。 在进行老化试验时，外部电源电压供给线与第一和第二内部电源电压供给线连接。 因此，第一和第二内部电源电压供给线直接接收外部电源电压。 这允许有效的老化测试。 在老化测试中，第一和第二降压转换器失效。

公开(公告)号：US08772694B2

公开(公告)日：2014-07-08

申请号：US13277921

申请日：2011-10-20

申请人： Hiroki Sugano ,  Fukashi Morishita

发明人： Hiroki Sugano ,  Fukashi Morishita

IPC分类号： H01L27/146 ,  G01J1/44

CPC分类号： H04N5/3532 ,  H04N5/3745 ,  H04N5/376

摘要： An image sensor with a small circuit area is provided. In the image sensor, a TX decoder which generates transfer signals TX includes a latch circuit. The latch circuit is set when a corresponding row group is selected and when a set signal is set to an “H” level, and is reset when a reset signal is set to an “L” level. The latch circuit serves also as a voltage level shift circuit which converts the “H” level of a signal from a first power supply voltage into a second power supply voltage. Therefore, plural row groups can be selected by setting plural latch circuits. It is not necessary to provide a voltage level shift circuit separately.

摘要翻译： 提供具有小电路面积的图像传感器。 在图像传感器中，产生传送信号TX <3：0>的TX解码器包括锁存电路。 当选择相应的行组并且将设置信号设置为“H”电平时，锁存电路被设置，并且当复位信号被设置为“L”电平时，锁存电路被复位。 锁存电路还用作电压电平移位电路，其将来自第一电源电压的信号的“H”电平转换为第二电源电压。 因此，可以通过设置多个锁存电路来选择多个行组。 不需要单独提供电压电平移位电路。

公开(公告)号：US20130010513A1

公开(公告)日：2013-01-10

申请号：US13621078

申请日：2012-09-15

申请人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US08164934B2

公开(公告)日：2012-04-24

申请号：US12720561

申请日：2010-03-09

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以增加搜索操作速度。

公开(公告)号：US07804368B2

公开(公告)日：2010-09-28

申请号：US12155876

申请日：2008-06-11

申请人： Masanobu Kishida ,  Fukashi Morishita

发明人： Masanobu Kishida ,  Fukashi Morishita

IPC分类号： H03B27/00

CPC分类号： H03K3/0315 ,  H03K17/063

摘要： The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.

摘要翻译： 本发明提供一种即使在以低电源电压驱动的情况下也能够稳定工作的电流限制型振荡器和使用该振荡器的电荷泵电路。 限流振荡器具有延迟部分，该延迟部分包括多个串联的反相器，用于基于限流电平指示信号来延迟输出脉冲，并且该振荡器还包括至少一个第一晶体管，其限制第一电流 所述逆变器和高电位电源以及限制所述逆变器之间的第二电流和低电位电源的至少一个第二晶体管，其中所述多个逆变器中的至少一个被配置为与所述第一逆变器连接的第一逆变器 并且不与第二晶体管连接，并且多个反相器中的至少另一个被配置为不与第一晶体管连接并与第二晶体管连接的第二反相器。

公开(公告)号：US20100109761A1

公开(公告)日：2010-05-06

申请号：US12683838

申请日：2010-01-07

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G05F1/10

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US20090058543A1

公开(公告)日：2009-03-05

申请号：US12289230

申请日：2008-10-23

申请人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

发明人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

IPC分类号： G01K7/00

CPC分类号： G01K7/01

摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.

摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。

公开(公告)号：US07459983B2

公开(公告)日：2008-12-02

申请号：US11452317

申请日：2006-06-14

申请人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

发明人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

IPC分类号： G01K7/00

CPC分类号： G01K7/01

摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.

摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。

公开(公告)号：US07456680B2

公开(公告)日：2008-11-25

申请号：US11135488

申请日：2005-05-24

申请人： Takayuki Gyohten ,  Fukashi Morishita

发明人： Takayuki Gyohten ,  Fukashi Morishita

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F1/465

摘要： A voltage for reference at a voltage level higher than a target value is produced from a constant current provided from a constant current generating circuit, and is subjected to resistance division by a resistance division circuit to produce a reference voltage at the target level, and then a final reference voltage is produced by a voltage follower. An internal voltage generating circuit thus provided can generate the reference voltage having the desired voltage level with high accuracy as well as an internal voltage based on the reference voltage by controlling temperature characteristic even with a low power supply voltage.

摘要翻译： 在从恒定电流产生电路提供的恒定电流中产生高于目标值的电压电压的参考电压，并通过电阻分割电路进行电阻分割以产生目标电平的参考电压，然后 最终的参考电压由电压跟随器产生。 由此提供的内部电压产生电路即使在低电源电压下也可以通过控制温度特性，以高精度产生具有所需电压电平的基准电压以及基于参考电压的内部电压。

公开(公告)号：US20070263466A1

公开(公告)日：2007-11-15

申请号：US11797804

申请日：2007-05-08

申请人： Fukashi Morishita ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： G11C7/02

CPC分类号： G11C7/14 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/7841

摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).

摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。