公开(公告)号：US6028446A

公开(公告)日：2000-02-22

申请号：US118200

申请日：1998-07-17

申请人： Om P. Agrawal ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Kerry A. Ilgenstein

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1774

摘要： A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the appropriate product term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.

摘要翻译： 可编程逻辑器件（PLD）单元用于构建高密度高性能可编程逻辑器件（PLD）。 PLD单元包括两个可编程逻辑块单元。 PLD单元还包括I / O单元和输入宏单元。 此外，PLD单元包括可编程输出开关矩阵组的子组和可编程输入开关矩阵组的子组。 每个可编程逻辑块单元包括多个乘积项。 集群中至少有一个产品术语可编程地可用于集群。 当产品术语与集群断开连接时，产品术语用于控制逻辑宏单元输出信号或异步功能的极性。 因此，可编程可连接产品术语可用于同步或异步操作。 如果可编程可连接和可断开的产品术语连接到产品术语集群，则可编程逻辑块单元用于同步操作。 然而，由于每个产品项集合与逻辑宏单元相关联，所以逻辑宏单元可以通过简单地从产品项集群中断开适当的产品项并使用所需的异步功能的乘积项来单独配置用于异步操作。 因此，使用可编程逻辑块单元构建的单个PLD同时支持同步和异步操作。

公开(公告)号：US5990702A

公开(公告)日：1999-11-23

申请号：US995612

申请日：1997-12-22

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Giap H. Tran

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Giap H. Tran

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17744 ,  H03K19/17796

摘要： A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides routing of signals between the IOBs and VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. The IOBs are arranged along a top, left, bottom and right side of the plurality of VGBs. An IOB includes a 1) delay for timing input signals, 2) a configurable output latch which may be set or reset responsive to control signals, and 3) transistor for controlling a NOR line. The IOB is programmably configured to the inter-connect network which includes vertical and horizontal inter-connect channels comprising adjacent inter-connect lines. The IOB inputs are connected to adjacent inter-connect lines including 1) direct connect input lines from adjacent super-VGBs, 2) MaxL lines, and 3) dendrite lines from adjacent dendrites. The IOB outputs are connected to 1) MaxL lines, 2) dendrite lines in adjacent dendrites, 3) NOR lines, and 4) direct connect output lines to adjacent super-VGBs. Dendrites for routing signals along the periphery of the plurality of VGBs are positioned between the IOBs and super-VGBs. Dendrites include a plurality of I/O switchboxes and dendrite lines. The I/O switchboxes are coupled to vertical and horizontal inter-connect channels. The inter-connect network includes a direct connect architecture between IOBs and adjacent super-VGBs. Dedicated connections between corner and non-corner IOBs provide direct connect inputs and outputs to and from CBBs in a super-VGB.

摘要翻译： 现场可编程门阵列（FPGA）装置包括多个输入/输出块（IOB）和可变粒子块（VGB）。 互连网络提供IOB和VGB之间的信号路由。 VGB包括具有功能生成资源的多个L组织CBB（可配置逻辑块）。 IOB沿着多个VGB的顶部，左侧，底部和右侧布置。 IOB包括1）用于定时输入信号的延迟，2）响应于控制信号可以被设置或复位的可配置输出锁存器，以及3）用于控制NOR线路的晶体管。 IOB可编程地配置到包括相邻连接线之间的垂直和水平互连通道的互连网络。 IOB输入连接到相邻的互连线，包括1）直接连接相邻超VGB的输入线，2）MaxL线，以及3）相邻枝晶的枝晶线。 IOB输出连接到1）MaxL线，2）相邻枝晶中的枝晶线，3）NOR线，以及4）将输出线直接连接到相邻的超VGB。 沿着多个VGB的周边路由信号的树枝状晶体位于IOB和超级VGB之间。 树枝包括多个I / O开关盒和枝晶线。 I / O开关盒耦合到垂直和水平互连通道。 互连网络包括IOB和相邻超级VGB之间的直接连接体系结构。 转角和非拐角IOB之间的专用连接可在超级VGB中向CBB提供直接连接输入和输出。

公开(公告)号：US5789939A

公开(公告)日：1998-08-04

申请号：US653186

申请日：1996-05-24

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler

IPC分类号： H03K19/177 ,  H03K19/082 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17704

摘要： A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchial level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.

摘要翻译： 一种非常高密度的复杂可编程逻辑器件（CPLD）具有多个层级信号路径。 层次结构的最低层次与所有更高层次是独立的。 类似地，中间级别与所有较高级别无关，并且仅利用与最低和中级层级相关联的CPLD的资源。 第一层级资源包括具有多个输入线和多条输出线的可编程逻辑块以及连接到可编程逻辑块的多条输入线的可编程块开关矩阵。 第二层级资源包括连接到可编程块开关矩阵的多个输入线的可编程段开关矩阵。 CPLD另外包括具有连接到第二层级资源的第三层级资源的第三层级电路，其中第三层级信号路径利用第三，第二和第一层级资源。 第三层级资源包括可编程全局开关矩阵，其具有可编程地连接到可编程段开关矩阵的线路并与其断开的全局开关矩阵线。

公开(公告)号：US5587921A

公开(公告)日：1996-12-24

申请号：US560933

申请日：1995-11-20

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a lookup table having inputs and outputs, a first multiplexer means for applying a selected subset of CLB input signals to the lookup table inputs, and a second multiplexer means for routing lookup table output signals to selectable destinations. The first multiplexer means can programmably route input signals to the lookup table inputs from a variety of sources including first through fourth direct-connect receiving terminals distributed symmetrically about the CLB, first through fourth longline receiving terminals distributed symmetrically about the CLB, first through fourth general-interconnect receiving terminals distributed symmetrically about the CLB, and first through fourth feedback means distributed symmetrically within the CLB. The second multiplexer means can programmably route output signals from the lookup table to first through fourth output macrocells distributed symmetrically about the CLB. The first through fourth output macrocells can respectively couple the routed signals to first through fourth direct-connect outputting terminals distributed symmetrically about the CLB, first through fourth tristate outputting terminals distributed symmetrically about the CLB, and the first through fourth feedback means.

摘要翻译： 可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。 每个CLB包括具有输入和输出的查找表，用于将选定的CLB输入信号的子集应用于查找表输入的第一多路复用器装置和用于将查找表输出信号路由到可选目的地的第二多路复用器装置。 第一多路复用器装置可编程地将输入信号路由到各种源的查找表输入，包括关于CLB对称分布的第一至第四直接接收终端，关于CLB对称分布的第一至第四延长线接收终端，第一至第四通用 - 关于CLB对称分布的接收端子以及在CLB内对称分布的第一至第四反馈装置。 第二多路复用器装置可编程地将来自查找表的输出信号路由到关于CLB对称分布的第一到第四输出宏小区。 第一到第四输出宏单元可以分别将路由信号耦合到关于CLB对称地分布的第一到第四直接连接输出端子，关于CLB对称地分布的第一到第四三态输出端子以及第一到第四反馈装置。

公开(公告)号：US5426335A

公开(公告)日：1995-06-20

申请号：US85601

申请日：1993-06-30

申请人： Om P. Agrawal ,  Kerry A. Ingenstein

发明人： Om P. Agrawal ,  Kerry A. Ingenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

公开(公告)号：US5359536A

公开(公告)日：1994-10-25

申请号：US25551

申请日：1993-03-03

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

公开(公告)号：US5261116A

公开(公告)日：1993-11-09

申请号：US891603

申请日：1992-06-01

申请人： Om P. Agrawal

发明人： Om P. Agrawal

IPC分类号： G06F9/22 ,  G06F9/26

CPC分类号： G06F9/223 ,  G06F9/264

摘要： A programmable controller which combines microaddress control logic, memory, a microinstruction decoder, and I/O into a unitary, integrated device. The microaddress control logic is responsive to sequencing signals developed by the microinstruction decoder, and includes an address generator which develops the program address. The memory, which can be either PROM or RAM, is addressed by the address and outputs a microinstruction word to a pipeline register. The microinstruction word has an internal field which is coupled to inputs of the microaddress control logic and the microinstruction decoder, and a control field which is coupled to an output buffer. The output buffer includes multiplexers which permit either the program count or the control field to be multiplexed to the output pins of the device. When the program address is multiplexed to the output pins, the programmable controller can address external memory devices.

摘要翻译： 可编程控制器，将微地址控制逻辑，存储器，微指令解码器和I / O组合到一体的集成器件中。 微地址控制逻辑响应于由微指令解码器开发的排序信号，并且包括开发程序地址的地址发生器。 存储器可以是PROM或RAM，由地址寻址，并将微指令字输出到流水线寄存器。 微指令字具有耦合到微地址控制逻辑和微指令解码器的输入的内部场，以及耦合到输出缓冲器的控制场。 输出缓冲器包括允许程序计数或控制字段复用到器件的输出引脚的多路复用器。 当程序地址复用到输出引脚时，可编程控制器可以寻址外部存储器件。

公开(公告)号：US5260881A

公开(公告)日：1993-11-09

申请号：US442528

申请日：1989-11-27

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17792

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

摘要翻译： 具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。 互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。 此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。 相反，未提交的长行致力于连接到互连的其他段。 互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。 可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。 互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。

公开(公告)号：US5233539A

公开(公告)日：1993-08-03

申请号：US429125

申请日：1989-10-30

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/17792

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

摘要翻译： 具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。 互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。 此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。 相反，未提交的长行致力于连接到互连的其他段。 互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。 可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。 互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。

公开(公告)号：US5179716A

公开(公告)日：1993-01-12

申请号：US370148

申请日：1989-06-21

申请人： Om P. Agrawal ,  Arthur H. Khu ,  William Chen

发明人： Om P. Agrawal ,  Arthur H. Khu ,  William Chen

IPC分类号： G06F9/22 ,  G06F9/26

CPC分类号： G06F9/264 ,  G06F9/223

摘要： A programmable controller which combines microaddress control logic, memory, a microinstruction decoder, and I/O into a unitary, integrated device. The microaddress control logic is responsive to sequencing signals developed by the microinstruction decoder, and includes an address generator which develops the program address. The memory, which can be either PROM or RAM, is addressed by the address and outputs a microinstruction word to a pipeline register. The microinstruction word has an internal field which is coupled to inputs of the microaddress control logic and the microinstruction decoder, and a control field which is coupled to an output buffer. The output buffer includes multiplexers which permit either the program count or the control field to be multiplexed to the output pins of the device. When the program address is multiplexed to the output pins, the programmable controller can address external memory devices.

摘要翻译： 可编程控制器，将微地址控制逻辑，存储器，微指令解码器和I / O组合到一体的集成器件中。 微地址控制逻辑响应于由微指令解码器开发的排序信号，并且包括开发程序地址的地址发生器。 存储器可以是PROM或RAM，由地址寻址，并将微指令字输出到流水线寄存器。 微指令字具有耦合到微地址控制逻辑和微指令解码器的输入的内部场，以及耦合到输出缓冲器的控制场。 输出缓冲器包括允许程序计数或控制字段复用到器件的输出引脚的多路复用器。 当程序地址复用到输出引脚时，可编程控制器可以寻址外部存储器件。