公开(公告)号：US08102704B2

公开(公告)日：2012-01-24

申请号：US12662247

申请日：2010-04-07

申请人： Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

发明人： Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

IPC分类号： G11C16/32

CPC分类号： G11C7/04 ,  G11C7/18 ,  G11C7/22 ,  G11C16/32 ,  G11C2207/002

摘要： Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

摘要翻译： 公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。 根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。 基于检查结果修改写操作信号。

公开(公告)号：US08040716B2

公开(公告)日：2011-10-18

申请号：US12613136

申请日：2009-11-05

申请人： Byung-Gil Choi ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0028 ,  G11C8/08 ,  G11C8/14 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72

摘要： A method of controlling the voltage of a sub-wordline in a variable resistive memory device includes switchably passing a voltage from a main wordline to the sub-wordline, and substantially blocking forward current flow from the sub-wordline to a variable resistive memory cell of the device.

摘要翻译： 一种控制可变电阻存储器件中的子字线电压的方法包括将电压从主字线切换到通过子字线，并且基本上阻止从副字线到可变电阻存储器单元的正向电流 装置。

公开(公告)号：US07952956B2

公开(公告)日：2011-05-31

申请号：US12417679

申请日：2009-04-03

申请人： Qi Wang ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Hyun-Ho Choi

发明人： Qi Wang ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Hyun-Ho Choi

IPC分类号： G11C8/00

CPC分类号： G11C16/08 ,  G11C8/12

摘要： A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

摘要翻译： 半导体存储器件包括具有分成第一和第二区域的多个可变电阻存储单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

公开(公告)号：US07936619B2

公开(公告)日：2011-05-03

申请号：US12339204

申请日：2008-12-19

申请人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

发明人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

IPC分类号： G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

摘要翻译： 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元 使用外部提供的升压电压。

公开(公告)号：US07889545B2

公开(公告)日：2011-02-15

申请号：US12187550

申请日：2008-08-07

申请人： Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C7/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2211/5622 ,  G11C2211/5641 ,  G11C2213/72 ,  G11C2213/79

摘要： An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.

摘要翻译： 使用具有三电平非易失性存储单元的非易失性存储器件的装置和操作方法在非易失性存储单元中存储多于一位的数据。 此外，可以通过写入验证操作来选择性地写入数据，从而提高写入操作的可靠性。 操作方法包括提供具有第一至第三非易失性存储单元的存储单元阵列，其中每个存储单元能够分别在第一数据与第一至第三电阻电平对应的第三数据之间存储一个存储单元。 每个阻力水平彼此不同。 在写入操作的第一间隔期间，分别将第一和第三数据写入第一和第三非易失性存储器单元。 在写入操作的第二间隔期间，将第二数据写入第二非易失性存储单元。

公开(公告)号：US07885098B2

公开(公告)日：2011-02-08

申请号：US11316017

申请日：2005-12-23

申请人： Yu-Hwan Ro ,  Woo-Yeong Cho ,  Byung-Gil Choi

发明人： Yu-Hwan Ro ,  Woo-Yeong Cho ,  Byung-Gil Choi

IPC分类号： G11C11/00

CPC分类号： G11C5/145 ,  G11C5/143 ,  G11C7/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2213/72

摘要： In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series between a word line and a bit line among the plurality of word lines and bit lines of the phase-change memory cell array. The memory device of this aspect further includes a sense node which is selectively connected to a bit line of the phase-change memory cell array, a boosting circuit which generates a boosted voltage which is greater than an internal power supply voltage, a pre-charge and biasing circuit which is driven by the boosted voltage to pre-charge and bias the sense node, and a sense amplifier connected to the sense node. The boosted voltage may be equal to or greater than a sum of the internal power supply voltage and a threshold voltage of the diode of each phase-change memory cell.

摘要翻译： 一方面，一种非易失性半导体存储器件包括：相位相变存储单元阵列，包括多个字线，多个位线和多个相变存储器单元，其中每个相变存储器 单元包括在相变存储单元阵列的多个字线和位线之间串联连接在字线和位线之间的相变电阻元件和二极管。 该方面的存储装置还包括有选择地连接到相变存储单元阵列的位线的感测节点，产生大于内部电源电压的升压电压的升压电路，预充电 以及由升压电压驱动以对感测节点进行预充电和偏置的偏置电路，以及连接到感测节点的读出放大器。 升压电压可以等于或大于内部电源电压和每个相变存储单元的二极管的阈值电压之和。

公开(公告)号：US07796425B2

公开(公告)日：2010-09-14

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C11/4193 ,  G11C11/4197

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US07656719B2

公开(公告)日：2010-02-02

申请号：US11898045

申请日：2007-09-07

申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

公开(公告)号：US07643335B2

公开(公告)日：2010-01-05

申请号：US11949342

申请日：2007-12-03

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲产生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

公开(公告)号：US07633788B2

公开(公告)日：2009-12-15

申请号：US11750802

申请日：2007-05-18

申请人： Byung-Gil Choi ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0028 ,  G11C8/08 ,  G11C8/14 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72

摘要： A variable resistive memory device includes a main wordline, a wordline connecting switch in signal communication with the main wordline, a sub-wordline in signal communication with the wordline connecting switch, and a variable resistive memory cell having a variable resistance in signal communication with a first terminal of a switching element, a second terminal of the switching element disposed in signal communication with the sub-wordline; and a method of controlling the voltage of a sub-wordline in a variable resistive memory device includes switchably passing a voltage from a main wordline to the sub-wordline, and substantially blocking forward current flow from the sub-wordline to a variable resistive memory cell of the device.

摘要翻译： 一种可变电阻式存储器件包括主字线，与主字线信号通信的字线连接开关，与字线连接开关信号通信的子字线，以及具有可变电阻的可变电阻存储器单元， 开关元件的第一端子，与所述副字线信号通信设置的所述开关元件的第二端子; 并且一种控制可变电阻存储器件中的子字线的电压的方法包括：可切换地将电压从主字线传递到子字线，并且基本上阻挡从子字线到可变电阻存储器单元的正向电流 的设备。