公开(公告)号：US20180314250A1

公开(公告)日：2018-11-01

申请号：US15581133

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Brian T. Lewis ,  Feng Chen ,  Jeffrey R. Jackson ,  Justin E. Gottschlich ,  Rajkishore Barik ,  Xiaoming Chen ,  Prasoonkumar Surti ,  Mike B. Macpherson ,  Murali Sundaresan

IPC: G05D1/00 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/063 ,  B60W30/095 ,  G01C21/34 ,  G06N3/008 ,  G06N3/0454

Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.

公开(公告)号：US20180308450A1

公开(公告)日：2018-10-25

申请号：US15493606

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Eric J. Hoekstra ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Eric G. Liskay ,  Joydeep Ray ,  Michael J. Norris ,  Wenyin Fu ,  Altug Koker

IPC: G09G5/02

CPC classification number: G09G5/02 ,  G09G2340/06 ,  G09G2350/00

Abstract: Methods and apparatus relating to techniques for provision of color mapping for better compression ratio are described. In an embodiment, a plurality of bits are moved from all channels of a first Red Green Blue Alpha (RGBA) space to an alpha channel of a second RGBA space. The plurality of the bits are selected from higher order bits of the first RGBA space. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180308208A1

公开(公告)日：2018-10-25

申请号：US15819093

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G06F17/16

CPC classification number: G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F17/16 ,  G06F2009/45583 ,  G06T1/60

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type

公开(公告)号：US20180307981A1

公开(公告)日：2018-10-25

申请号：US15494826

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Gokcen Cilingir ,  Elmoustapha Ould-Ahmed-Vall ,  Rajkishore Barik ,  Kevin Nealis ,  Xiaoming Chen ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Nilesh Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/46 ,  G06N3/04 ,  G06N3/063 ,  G06T1/20

Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.

公开(公告)号：US20180307485A1

公开(公告)日：2018-10-25

申请号：US15493467

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Ramkumar Ravikumar ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F13/36 ,  G06F13/40

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300933A1

公开(公告)日：2018-10-18

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US20180293961A1

公开(公告)日：2018-10-11

申请号：US15483748

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Atsuo Kuwahara ,  Sameer Kp ,  Jonathan Kennedy

IPC: G09G5/36 ,  G06T15/00 ,  G06T1/60 ,  G09G5/39 ,  G06F13/16

Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.

公开(公告)号：US20180293011A1

公开(公告)日：2018-10-11

申请号：US15482971

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Prasoonkumar Surti ,  Aravindh V. Anantaraman ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu

IPC: G06F3/06 ,  G06F1/32 ,  G11C11/406

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a memory comprising one or more physical memory chips, and a processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips. The working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set.

公开(公告)号：US20180268597A1

公开(公告)日：2018-09-20

申请号：US15988157

申请日：2018-05-24

Applicant: Intel Corporation

Inventor： Bimal Poddar ,  Prasoonkumar Surti ,  Rahul P. Sathe

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/60 ,  G06T15/04 ,  G06T19/20

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/04 ,  G06T15/506 ,  G06T19/20 ,  G06T2200/04 ,  G06T2200/28 ,  G06T2210/62

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

公开(公告)号：US09053040B2

公开(公告)日：2015-06-09

申请号：US14471106

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti

IPC: G09G5/36 ,  G06T1/60 ,  G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/401 ,  G06F2212/455 ,  G06T1/60 ,  G06T2200/28 ,  G09G5/36 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/122

Abstract: Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may be checked to see whether both a subspan request hits an unlit bit and a modify message was already sent. If so, the modification message may be filtered.

Abstract translation: 可以对修改消息进行过滤，以减少渲染缓存和帧缓冲区压缩之间的消息通道的负载。 可以检查一组高速缓存行，以查看子跨越请求是否触发不亮位，并且已经发送修改消息。 如果是这样，可以对修改消息进行过滤。