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    STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES
    91.
    发明申请
    STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES 有权
    半导体功率器件的结构与方法

    公开(公告)号：US20110133275A1

    公开(公告)日：2011-06-09

    申请号：US13028054

    申请日：2011-02-15

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L27/06

    CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/78624

    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.

    Abstract translation: 半导体器件包括在衬底上的绝缘体上半导体区域。 绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。 该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。 该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。 双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。 因此，MOS晶体管的漏极也用作双极晶体管的发射极。 此外，栅极和基极通过电阻元件耦合。

    Structure and method for semiconductor power devices
    92.
    发明授权
    Structure and method for semiconductor power devices 有权
    半导体功率器件的结构和方法

    公开(公告)号：US07910995B2

    公开(公告)日：2011-03-22

    申请号：US12109293

    申请日：2008-04-24

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L27/12

    CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/78624

    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.

    Abstract translation: 半导体器件包括在衬底上的绝缘体上半导体区域。 绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。 该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。 该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。 双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。 因此，MOS晶体管的漏极也用作双极晶体管的发射极。 此外，栅极和基极通过电阻元件耦合。

    High density trench field effect transistor
    94.
    发明申请
    High density trench field effect transistor 有权
    高密度沟槽场效应晶体管

    公开(公告)号：US20100065904A1

    公开(公告)日：2010-03-18

    申请号：US12211654

    申请日：2008-09-16

    Applicant: James Pan ,  Scott L. Hunt ,  Dean E. Probst ,  Hossein Paravi

    Inventor： James Pan ,  Scott L. Hunt ,  Dean E. Probst ,  Hossein Paravi

    IPC: H01L29/78

    CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397

    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.

    Abstract translation: 半导体结构包括延伸到半导体区域中的沟槽。 半导体区域的部分在形成台面区域的相邻沟槽之间延伸。 栅电极在每个沟槽中。 第一导电类型的阱区在相邻沟槽之间的半导体区域中延伸。 第二导电类型的源极区位于阱区中。 第一导电类型的重体区域在井区域中。 源极区域和重体区域是相邻的沟槽侧壁，并且重体区域沿着沟槽侧壁延伸到源区域上方到台面区域的顶表面。

    Structure and Method for Forming Power Devices with High Aspect Ratio Contact Openings
    96.
    发明申请
    Structure and Method for Forming Power Devices with High Aspect Ratio Contact Openings 有权
    用于形成具有高纵横比接触开口的功率器件的结构和方法

    公开(公告)号：US20090189218A1

    公开(公告)日：2009-07-30

    申请号：US12333597

    申请日：2008-12-12

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    Abstract: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric layer. Contact openings extend into the body regions between adjacent gate electrodes. A seed layer extends along the bottom of each contact opening. The seed layer serves as a nucleation site for promoting growth of conductive fill material. A conductive fill material fills a lower portion of each contact opening. An interconnect layer fills an upper portion of each contact opening and is in direct contact with the conductive fill material. The interconnect layer is also in direct contact with corresponding source regions along upper sidewalls of the contact openings.

    Abstract translation: 场效应晶体管（FET）包括在第二导电类型的半导体区域上的第一导电类型的体区。 第二导电类型的源区域在身体区域上延伸。 栅电极通过栅极介电层相邻延伸而与体区绝缘。 接触开口延伸到相邻栅电极之间的主体区域。 种子层沿着每个接触开口的底部延伸。 种子层用作促进导电填充材料生长的成核位点。 导电填充材料填充每个接触开口的下部。 互连层填充每个接触开口的上部并与导电填充材料直接接触。 互连层也沿着接触开口的上侧壁的相应源极区直接接触。

    Structure and Method for Forming Shielded Gate Trench FET with Multiple Channels
    99.
    发明申请
    Structure and Method for Forming Shielded Gate Trench FET with Multiple Channels 有权
    用于形成具有多个通道的屏蔽栅极沟道FET的结构和方法

    公开(公告)号：US20090166728A1

    公开(公告)日：2009-07-02

    申请号：US11964283

    申请日：2007-12-26

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7831

    Abstract: A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

    Abstract translation: 场效应晶体管（FET）包括延伸到半导体区域中的一对沟槽。 每个沟槽包括在沟槽的下部中的第一屏蔽电极和在沟槽的上部中的与屏蔽电极绝缘的栅电极。 第一导电类型的第一和第二阱区域在该对沟槽之间的半导体区域中横向延伸并邻接该对沟槽的侧壁。 第一和第二阱区域通过第二导电类型的第一漂移区域彼此垂直间隔开。 栅电极和第一屏蔽电极相对于第一阱区和第二阱区定位，使得当FET被置于导通状态时，在第一和第二阱区中的每一个中形成沟道。

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