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公开(公告)号：US09246519B2
公开(公告)日：2016-01-26
申请号：US13672218
申请日：2012-11-08
Applicant: LSI Corporation
Inventor： Jefferson E. Singleton , Shaohua Yang , Bruce A. Wilson , Keenan T. O'Brien
IPC: G06F11/263 , H03M13/00 , H03M13/11 , H03M13/35
CPC classification number: H03M13/6356 , H03M13/11 , H03M13/35 , H03M13/63 , H03M13/6343
Abstract: A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium.
Abstract translation: 一种用于在基于LDPC的驱动系统中产生用于媒体的LDPC编码测试模式的方法，包括将误差检测码数据添加到主要为零比特的测试模式，并且添加额外的零比特以产生期望长度的测试模式。 然后可以对测试图案进行加扰以产生所需的探伤测试图案。 然后，探伤测试模式可以用LDPC码或其他纠错码进行编码，对数据模式的游程长度限制具有最小干扰，并写入存储介质。
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公开(公告)号：US20160020783A1
公开(公告)日：2016-01-21
申请号：US14334125
申请日：2014-07-17
Applicant: LSI Corporation
Inventor： Shaohua Yang , Shu Li , Dan Liu , Qi Zuo
CPC classification number: H03M13/114 , G11B20/1833 , G11B2020/185 , H03M13/1108 , H03M13/1122 , H03M13/116 , H03M13/451 , H03M13/458 , H03M13/6325 , H03M13/6577 , H03M13/658
Abstract: An apparatus for low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to update variable node values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages based on the variable node to check node messages. The variable node processor and the check node processor comprise a quasi-cyclic decoder with relative indexes that refer to non-zero circulants.
Abstract translation: 用于低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点将可变节点值更新到可变节点消息。 校验节点处理器可操作以基于变量节点向可变节点消息生成校验节点，以校验节点消息。 可变节点处理器和校验节点处理器包括具有参考非零循环的相对索引的准循环解码器。
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公开(公告)号：US09214959B2
公开(公告)日：2015-12-15
申请号：US13770008
申请日：2013-02-19
Applicant: LSI Corporation
Inventor： Shaohua Yang , Fan Zhang , Chung-Li Wang , Shu Li
CPC classification number: H03M13/1122 , G11B20/1833 , H03M13/1128 , H03M13/114 , H03M13/1142 , H03M13/6331 , H03M13/6343 , H03M13/658
Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process. In one embodiment a data processing system includes a skip control circuit operable to skip re-application of a data decode algorithm to a portion of a codeword where at least the number of unsatisfied checks for the portion is zero.
Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法，包括在数据解码过程中跳过一个或多个码字块。 在一个实施例中，数据处理系统包括跳过控制电路，该跳过控制电路可操作以跳过将数据解码算法重新应用于代码字的至少部分的不满足检查数为零的部分。
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94.发明授权公开(公告)号：US09142251B2
公开(公告)日：2015-09-22
申请号：US14177496
申请日：2014-02-11
Applicant: LSI Corporation
Inventor： Yuqing Yang , Shaohua Yang , Lei Wang , Gu Zhao
CPC classification number: G11B20/10222 , G11B5/59616 , G11B5/59655 , G11B20/10296 , G11B2220/2516
Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for data synchronization and detection.
Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于数据同步和检测的系统和方法。
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公开(公告)号：US09123383B1
公开(公告)日：2015-09-01
申请号：US14197748
申请日：2014-03-05
Applicant: LSI Corporation
Inventor： Xuebin Wu , Shaohua Yang , Zhi Bin Li , Haitao Xia
CPC classification number: G11B20/1024 , G11B20/10037
Abstract: A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.
Abstract translation: 数据存储系统识别幅度低于某一阈值的模数转换样本。 剩余样品根据阶段分组成一个或多个象限。 使用具有重叠象限的多坐标来进一步区分采样点。 然后，该系统计算零相位开始估计的平均相位。
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Patent Agency Ranking
公开(公告)号：US09110821B2
公开(公告)日：2015-08-18
申请号：US14243107
申请日：2014-04-02
Applicant: LSI Corporation
Inventor： Weijun Tan , Fan Zhang , Shaohua Yang
CPC classification number: G06F11/10 , G11B20/10009 , G11B20/10287 , G11B20/10296 , G11B20/1816 , G11B20/1883
Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a method is discusses that includes: receiving a decoded output including a first multi-bit symbol; receiving a detected output including a second multi-bit bit symbol; calculating values based upon respective combinations of the first multi-bit symbol and the second multi-bit symbols; calculating a first product and the second product based upon some of the aforementioned values; and asserting a suspect symbol indicator indicating a probability that the symbol is incorrect when at least one of the first product and the second product is negative.
Abstract translation: 本发明的各种实施例提供了用于介质缺陷检测的系统和方法。 作为示例，讨论了一种方法，其包括：接收包括第一多位符号的解码输出; 接收包括第二多位位符号的检测输出; 基于第一多位符号和第二多位符号的相应组合计算值; 基于一些上述值计算第一产品和第二产品; 并且当第一产品和第二产品中的至少一个为负时，断定指示符号不正确的概率的可疑符号指示符。
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公开(公告)号：US09048874B2
公开(公告)日：2015-06-02
申请号：US13886103
申请日：2013-05-02
Applicant: LSI Corporation
Inventor： Chung-Li Wang , Zongwang Li , Shu Li , Fan Zhang , Shaohua Yang
CPC classification number: H03M13/13 , H03M13/1122 , H03M13/1125 , H03M13/1171 , H03M13/6583
Abstract: An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.
Abstract translation: 用于解码数据的装置包括可变节点处理器，校验节点处理器和场变换电路。 可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。 校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。 可变节点处理器和校验节点处理器包括不同的伽罗瓦域。 场变换电路可操作以将变量节点变换为将来自不同伽罗瓦域中的第一个的节点消息校验到伽罗瓦域中的第二个。
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公开(公告)号：US08996969B2
公开(公告)日：2015-03-31
申请号：US13708941
申请日：2012-12-08
Applicant: LSI Corporation
Inventor： Anatoli A. Bolotov , Shaohua Yang , Zongwang Li , Mikhail I Grinchuk , Lav D. Ivanovic , Fan Zhang , Yang Han
CPC classification number: H03M13/13 , H03M13/1111 , H03M13/1142
Abstract: A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.
Abstract translation: 数据处理系统包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。
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公开(公告)号：US08977926B2
公开(公告)日：2015-03-10
申请号：US13629726
申请日：2012-09-28
Applicant: LSI Corporation
Inventor： Chung-Li Wang , Lei Chen , Fan Zhang , Shaohua Yang , Qi Qi
CPC classification number: H03M13/1108 , H03M13/3738
Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.
Abstract translation: LDPC解码器包括用于不满足检查的LDPC码字中的可疑比特的目标符号翻转的处理器。 检查索引和可变索引的所有组合被编译并且相关联到目标符号翻转候选的池中，并且与符号索引一起返回到使用这样的符号索引来识别符号以便打破陷阱集合的过程。
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100.发明申请公开(公告)号：US20150062738A1
公开(公告)日：2015-03-05
申请号：US14025468
申请日：2013-09-12
Applicant: LSI Corporation
Inventor： Shaohua Yang
CPC classification number: H03M13/27 , G06F11/1076 , G11B20/1217 , G11B20/1866 , G11B20/1889 , H03M13/05 , H03M13/1102
Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.
Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于编码和解码信息的系统和方法。
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