公开(公告)号：US20250021130A1

公开(公告)日：2025-01-16

申请号：US18349976

申请日：2023-07-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciej Machnikowski

IPC: G06F1/12

Abstract: In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.

公开(公告)号：US12177325B2

公开(公告)日：2024-12-24

申请号：US18523991

申请日：2023-11-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.

公开(公告)号：US12079029B2

公开(公告)日：2024-09-03

申请号：US17313026

申请日：2021-05-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Itai Levy ,  Dotan David Levi ,  Nir Nitzani ,  Natan Manevich ,  Alex Vaynman ,  Ariel Almog

IPC: G06F1/12 ,  G06F13/20 ,  H04L7/00

CPC classification number: G06F1/12 ,  G06F13/20 ,  H04L7/0012

Abstract: A network adapter includes a network port for communicating with a communication network, a hardware clock, and circuitry. The circuitry is coupled to receive from the communication network, via the network port, one or more time-protocol packets that convey a network time used for synchronizing network devices in the communication network, to align the hardware clock to the network time conveyed in the time-protocol packets, and to make the network time available to one or more time-service consumers running in a host served by the network adapter.

公开(公告)号：US20240281292A1

公开(公告)日：2024-08-22

申请号：US18110788

申请日：2023-02-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Shay Aisman ,  Ariel Almog ,  Eliel Peretz ,  Igor Voks

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/505

Abstract: A device includes a transceiver coupled to a processing device. The processing device is to determine a first time for executing an operation associated with a work execution agent of a plurality of work execution agent. The processing device is further to receive a latency measurement associated with the work execution agent responsive to transmitting the request. The latency measurement is calculated after executing a previous operation associated with the work execution agent at the device. The processing device is also to modify the first time to a second time for executing the operation responsive to receiving the latency measurement.

公开(公告)号：US12058309B2

公开(公告)日：2024-08-06

申请号：US16291023

申请日：2019-03-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

IPC: H04N19/105 ,  H04N19/139 ,  H04N19/147 ,  H04N19/176

CPC classification number: H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/147

Abstract: A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce a score of result blocks based on similarity of each the block in each frame to be encoded to every block of the reference frame, and a displacement vector. Related apparatus and methods are also provided.

公开(公告)号：US20240244227A1

公开(公告)日：2024-07-18

申请号：US18096424

申请日：2023-01-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Eshed Ram ,  Dotan David Levi ,  Assaf Hallak ,  Shie Mannor ,  Gal Chechik ,  Eyal Frishman ,  Ohad Markus ,  Dror Porat ,  Assaf Weissman

IPC: H04N19/149 ,  H04N19/154 ,  H04N19/172

CPC classification number: H04N19/149 ,  H04N19/154 ,  H04N19/172

Abstract: A system includes a processing device to receive a video content, a quality metric, and a target bit rate for encoding the video content. The system includes encoding hardware to perform frame encoding on the video content and a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the quality metric and the target bit rate. The controller is further programmed to provide the first QP values to the encoding hardware for rate control of the frame encoding.

公开(公告)号：US20240193106A1

公开(公告)日：2024-06-13

申请号：US18444804

申请日：2024-02-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US20240134731A1

公开(公告)日：2024-04-25

申请号：US18074751

申请日：2022-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0736

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

公开(公告)号：US11940933B2

公开(公告)日：2024-03-26

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US20230409327A1

公开(公告)日：2023-12-21

申请号：US17844461

申请日：2022-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Eliel Peretz ,  Richard Graham ,  Daniel Marcovitch ,  Gil Bloch ,  Roee Moyal ,  Eyal Srebro ,  Sean Midthun Pieper

IPC: G06F9/30 ,  G06F9/445

CPC classification number: G06F9/30192 ,  G06F9/30025 ,  G06F9/44542

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include circuitry that collects data received from a data source, references a descriptor that describes a data reformat operation to perform on the data received from the data source, reformats the data received from the data source according to the data reformat operation, and provides the reformatted data to the data target via the second device interface.