公开(公告)号：US20240233869A9

公开(公告)日：2024-07-11

申请号：US18049498

申请日：2022-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G06F16/903

CPC classification number: G16B30/10 ,  G06F16/90339

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US20240232601A1

公开(公告)日：2024-07-11

申请号：US18582467

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F12/0646 ,  G06N3/04 ,  G06F2212/1008

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

公开(公告)号：US12021547B2

公开(公告)日：2024-06-25

申请号：US17677593

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10 ,  G11C15/04 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/1575 ,  G06F11/1068 ,  G11C15/04 ,  H03M13/43

Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.

公开(公告)号：US20240152292A1

公开(公告)日：2024-05-09

申请号：US18415285

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US20240136015A1

公开(公告)日：2024-04-25

申请号：US18049498

申请日：2022-10-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G06F16/903

CPC classification number: G16B30/10 ,  G06F16/90339

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US11869589B2

公开(公告)日：2024-01-09

申请号：US17188843

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.

公开(公告)号：US11829729B2

公开(公告)日：2023-11-28

申请号：US16888345

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Dmitri Yudanov ,  Sivagnanam Parthasarathy

IPC: G06F7/544 ,  G06F17/16

CPC classification number: G06F7/5443 ,  G06F17/16

Abstract: Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.

公开(公告)号：US11636893B2

公开(公告)日：2023-04-25

申请号：US17073621

申请日：2020-10-19

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Shivam Swami

IPC: G11C11/40 ,  G11C11/4093 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/408

Abstract: An example memory sub-system includes: a plurality bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each bank group; and a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving, from a host, a command identifying a row buffer of the plurality of row buffers; and perform an operation with respect to the identified row buffer.

公开(公告)号：US11556656B2

公开(公告)日：2023-01-17

申请号：US16582871

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06F21/60 ,  H03K19/21 ,  G06F21/79

Abstract: Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.

公开(公告)号：US20220391330A1

公开(公告)日：2022-12-08

申请号：US17888392

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean Stephen Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F13/10 ,  G06F3/06 ,  G06F13/12 ,  G06F12/0802

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.