公开(公告)号：US20180323133A1

公开(公告)日：2018-11-08

申请号：US15584278

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/48 ,  H01L49/02 ,  H01L23/482 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L23/482 ,  H01L23/5384 ,  H01L28/10 ,  H01L2223/58

Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.

公开(公告)号：US10121739B1

公开(公告)日：2018-11-06

申请号：US15584881

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5227 ,  H01L23/481

Abstract: A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed around the first TSV. The second die includes a second TSV coupled to the first TSV and a second substantially helical conductor disposed around the second TSV. The first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.

公开(公告)号：US20180166317A1

公开(公告)日：2018-06-14

申请号：US15882821

申请日：2018-01-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L29/66 ,  H01L21/265 ,  H01L21/768

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20180122762A1

公开(公告)日：2018-05-03

申请号：US15339693

申请日：2016-10-31

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Kyle K. Kirby ,  Owen R. Fay ,  Sameer S. Vadhavkar

IPC: H01L23/00 ,  H01L23/24 ,  H01L21/56

Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.

公开(公告)号：US09514975B2

公开(公告)日：2016-12-06

申请号：US14755274

申请日：2015-06-30

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/108 ,  H01L23/498 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20150028476A1

公开(公告)日：2015-01-29

申请号：US14514184

申请日：2014-10-14

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/014

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.

Abstract translation: 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括在半导体器件的前侧形成一个或多个开口，并且在部分填充开口的开口中形成牺牲塞。 该方法还包括用导电材料进一步填充部分填充的开口，其中各个牺牲插塞通常在导电材料和半导体器件的衬底之间。 牺牲插头暴露在半导体器件的背面。 可以通过去除牺牲塞在背面形成接触区域。

公开(公告)号：US20130221446A1

公开(公告)日：2013-08-29

申请号：US13850840

申请日：2013-03-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/498 ,  H01L29/78

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20250132265A1

公开(公告)日：2025-04-24

申请号：US18789128

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Mark Fischer

IPC: H01L23/544 ,  H01L23/498

Abstract: Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a first wafer having a front surface and a back surface opposite the front surface, and a second wafer having upper surface coupled to the back surface of the first wafer. The first wafer can also include one or more first alignment features. Each of the first alignment feature(s) can include a transparent material extending from the front surface to the back surface, thereby forming a window through the first wafer, allowing the location of conductive features on the front surface to be determined from the back surface using optical measurements. The second wafer can include one or more second alignment features that are positioned within a longitudinal footprint of a corresponding one of the first alignment features.

公开(公告)号：US12183716B2

公开(公告)日：2024-12-31

申请号：US17711583

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K Street ,  Kunal R. Parekh

IPC: H01L25/00 ,  H01L25/065

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

公开(公告)号：US12107050B2

公开(公告)日：2024-10-01

申请号：US17325090

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L27/0688 ,  H01L27/092

Abstract: Systems and methods for a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.