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公开(公告)号：US20250008750A1
公开(公告)日：2025-01-02
申请号：US18736187
申请日：2024-06-06
Applicant: Micron Technology, Inc.
Inventor： Wei Zhou , Kunal R. Parekh
IPC: H10B80/00 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
Abstract: A semiconductor device with a through via between redistribution layers is disclosed. The semiconductor device includes a stack of semiconductor dies coupled with first contact pads on a first redistribution layer. The first redistribution layer further includes a second contact pad located outside the footprint of the die stack and circuitry coupling the second contact pad to the first contact pads. A gap fill is disposed around the stack of semiconductor dies. A second redistribution layer is disposed at the stack of semiconductor dies and the gap fill. The second redistribution layer includes third contact pads coupled with the stack of semiconductor dies, a fourth contact pad disposed beyond the footprint of the stack of semiconductor dies, fifth contact pads opposite the third and fourth contact pads, and circuitry coupling the contact pads. A through via is disposed through the gap fill coupling the second and fourth contact pads.
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公开(公告)号：US20250006704A1
公开(公告)日：2025-01-02
申请号：US18736318
申请日：2024-06-06
Applicant: Micron Technology, Inc.
Inventor： Wei Zhou , Kunal R. Parekh
IPC: H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18 , H10B80/00
Abstract: A semiconductor device with a spaced supply voltage and ground reference is disclosed. A stack of semiconductor dies includes a first semiconductor die, one or more second semiconductor dies, and first and second contacts. A gap fill is disposed over a distal end of the one or more second semiconductor dies opposite the first semiconductor die. A first rail (e.g., supply voltage) is disposed at a distal end of the gap fill opposite the first semiconductor die, and a first via extends from the first rail to the first contact. A layer of dielectric material is disposed at least partially over the first rail. A second rail (e.g., ground reference) is disposed at the layer of dielectric material, and a second via extends from the second rail to the second contact. Third and fourth exposed contacts are coupled to the first and second rails, respectively.
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公开(公告)号：US20240413021A1
公开(公告)日：2024-12-12
申请号：US18668106
申请日：2024-05-17
Applicant: Micron Technology, Inc.
Inventor： Wei Zhou , Kunal R. Parekh
Abstract: Methods, apparatuses, and systems related to a semiconductor apparatus having one or more dielectric structures used to detect bonding voids during manufacturing. In some embodiments, a semiconductor wafer includes the dielectric structures. After the wafer is bonded to another structure, capacitances may be measured across the dielectric structures and the other wafer. The measured capacitance can be used to detect or characterize any bonding voids that may have been introduced during the wafer bonding process.
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公开(公告)号：US20240379503A1
公开(公告)日：2024-11-14
申请号：US18780303
申请日：2024-07-22
Applicant: Micron Technology, Inc.
Inventor： Wei Zhou , Kyle K. Kirby , Bret K. Street , Kunal R. Parekh
IPC: H01L23/48 , H01L21/768 , H01L23/00 , H01L25/065
Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.
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公开(公告)号：US20240373637A1
公开(公告)日：2024-11-07
申请号：US18771964
申请日：2024-07-12
Applicant: Micron Technology, Inc.
Inventor： Hongbin Zhu , Gurtej S. Sandhu , Kunal R. Parekh
Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.
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公开(公告)号：US12112793B2
公开(公告)日：2024-10-08
申请号：US17885374
申请日：2022-08-10
Applicant: Micron Technology, Inc.
Inventor： Aliasger T. Zaidy , Glen E. Hush , Sean S. Eilert , Kunal R. Parekh
IPC: G11C11/4093 , G06F3/06 , G06F13/16 , G06F13/28 , G11C7/08 , G11C7/10 , G11C11/408 , G11C11/4091 , G11C11/4096 , G16B30/00 , G16B50/10 , H01L21/66 , H01L21/78 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: G11C11/4093 , G06F3/0656 , G06F13/1673 , G06F13/28 , G11C7/08 , G11C7/1039 , G11C11/4087 , G11C11/4091 , G11C11/4096 , G16B30/00 , G16B50/10 , H01L21/78 , H01L22/12 , H01L24/08 , H01L24/48 , H01L24/80 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , G06F2213/28 , H01L24/16 , H01L2224/0801 , H01L2224/08145 , H01L2224/1601 , H01L2224/16221 , H01L2224/48091 , H01L2224/48145 , H01L2224/48221 , H01L2224/80895 , H01L2224/80896 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/1431 , H01L2924/14335 , H01L2924/1436
Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.
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公开(公告)号：US12068272B2
公开(公告)日：2024-08-20
申请号：US18059165
申请日：2022-11-28
Applicant: Micron Technology, Inc.
Inventor： Akira Goda , Kunal R. Parekh , Aaron S. Yip
CPC classification number: H01L24/20 , H01L24/03 , H01L24/05 , H01L24/19 , H01L25/18 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40 , H01L2924/1431 , H01L2924/1438
Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.
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公开(公告)号：US20240274562A1
公开(公告)日：2024-08-15
申请号：US18630883
申请日：2024-04-09
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Kunal R. Parekh , Beau D. Barry
IPC: H01L23/00 , G11C11/408 , G11C11/4091 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H01L24/08 , G11C11/4085 , G11C11/4091 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80896 , H01L2924/1431 , H01L2924/1436
Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.
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公开(公告)号：US12029032B2
公开(公告)日：2024-07-02
申请号：US18117989
申请日：2023-03-06
Applicant: Micron Technology, Inc.
Inventor： Justin B. Dorhout , Kunal R. Parekh , Martin C. Roberts , Mohd Kamran Akhtar , Chet E. Carter , David Daycock
IPC: H10B41/35 , H01L21/033 , H01L21/308 , H01L21/311 , H01L21/3215 , H01L21/67 , H01L21/768 , H10B20/00 , H10B41/20 , H10B41/23 , H10B41/27 , H10B43/27 , H10B43/35
CPC classification number: H10B41/35 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/3215 , H01L21/32155 , H01L21/67063 , H01L21/76802 , H10B20/383 , H10B41/20 , H10B41/23 , H10B41/27 , H10B43/27 , H01L2221/1063 , H10B43/35
Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
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10.发明公开
公开(公告)号：US20240063068A1
公开(公告)日：2024-02-22
申请号：US17892036
申请日：2022-08-19
Applicant: Micron Technology, Inc.
Inventor： Kunal R. Parekh , Bret K. Street , Terrence B. McDaniel , Jaekyu Song
IPC: H01L23/13 , H01L25/065 , H01L25/00 , H01L23/498 , H01L23/538
CPC classification number: H01L23/13 , H01L25/0652 , H01L25/50 , H01L23/49816 , H01L23/49833 , H01L23/5382 , H01L23/5385 , H01L23/5386 , H01L24/73
Abstract: A semiconductor device assembly comprises a package substrate including (i) an upper surface having a plurality of internal contacts, (ii) a lower surface having a plurality of external contacts coupled to the plurality of internal contacts, and (iii) a cavity extending into the package substrate. The assembly further comprises a stack of first semiconductor devices disposed in the cavity, an uppermost first semiconductor device of the stack having a plurality of stack contacts, and an interposer including (i) a bottom surface having a first plurality of lower contacts coupled to the plurality of stack contacts and a second plurality of lower contacts coupled to the plurality of internal contacts, and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts. The assembly further comprises a second semiconductor device including a plurality of die contacts coupled to the plurality of upper contacts.
