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    Graphic processor suitable for graphic data tranfers and conversion processes
    93.
    发明授权
    Graphic processor suitable for graphic data tranfers and conversion processes 失效
    图形处理器适用于图形数据传输和转换过程

    公开(公告)号：US5319750A

    公开(公告)日：1994-06-07

    申请号：US942001

    申请日：1992-09-08

    申请人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Nasakatu Yokoyama

    发明人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Nasakatu Yokoyama

    IPC分类号： G06T17/00 ,  G06F15/62

    CPC分类号： G06T17/00

    摘要： A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word. Even if transfer source graphic data lies across two consecutive words, the processor fetches the source data in single reading, processes the data word-wise at once, and stores the result in the display memory.

    摘要翻译： 用于控制用于存储图形数据的显示存储器的图形数据的读取，写入和传送的图形处理器。 处理器包括第一单元，其存储用于寻址显示存储器的第一地址信息和指向由第一地址信息指定的字中的像素位置的第一像素地址信息;第二单元，存储用于寻址显示存储器的第二地址信息;以及 指定由第二地址信息指定的字中的像素位置的第二像素地址信息;移动包括在两个连续字中的多个像素的图形数据以提取连续的1字图形数据的第三单元;以及实现绘图的第四单元 根据包含在一个单词中的像素数量，对一个单词进行像素同步的计算。 即使传输源图形数据位于两个连续的字中，处理器以单次读取的方式读取源数据，一次处理数据，并将结果存储在显示存储器中。

    Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory
    94.
    发明授权
    Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory 失效
    具有能够在帧缓冲器和系统存储器中进行高速并行绘制处理的总线连接控制的图形处理系统

    公开(公告)号：US5046023A

    公开(公告)日：1991-09-03

    申请号：US105292

    申请日：1987-10-06

    申请人： Koyo Katsura ,  Shigeru Matsuo ,  Jun Sato ,  Takashi Sone ,  Yoshikazu Yokota ,  Masahiko Kikuchi

    发明人： Koyo Katsura ,  Shigeru Matsuo ,  Jun Sato ,  Takashi Sone ,  Yoshikazu Yokota ,  Masahiko Kikuchi

    IPC分类号： G06T1/20 ,  G06T11/20 ,  G09G5/02 ,  G09G5/393 ,  G09G5/399

    CPC分类号： G09G5/393 ,  G06T1/20 ,  G06T11/203 ,  G09G5/024 ,  G09G5/399

    摘要： A graphic processing system including a main memory for storing a program and information corresponding to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively. The system also includes bus connection switch circuit to be controlled by the graphic processor to effect a connection control between the first and second address buses and between the first and second data buses so as to enable execution of a drawing processing in the main memory connected to a bus on the main processor side and a data transfer between the main memory and the frame buffer.

    摘要翻译： 一种图形处理系统，包括用于存储程序的主存储器和与像素相对应的信息，用于执行从主存储器或从外部设备传送的程序的执行处理以便控制系统的主处理器，显示/输出设备 例如用于输出通过控制以多个维度排列的像素获得的图形信息的CRT设备和打印机，用于存储对应于输出到显示/输出设备的像素的信息的帧缓冲器，以及用于接收命令和参数的图形处理器 从主存储器和/或主处理器传送的信息，用于根据预定的处理过程产生字符和图形数据，并且用于执行包括执行绘图处理的传送控制，以通过第一和第二地址总线传送生成的数据;以及 第一和第二数据总线到主存储器和/或帧缓冲器， 分别。 该系统还包括由图形处理器控制的总线连接开关电路，以实现第一和第二地址总线之间以及第一和第二数据总线之间的连接控制，以便能够执行连接到 主处理器侧的总线和主存储器与帧缓冲器之间的数据传输。

    Graphic processing apparatus
    96.
    发明授权
    Graphic processing apparatus 失效
    图形处理装置

    公开(公告)号：US4779210A

    公开(公告)日：1988-10-18

    申请号：US727850

    申请日：1985-04-26

    申请人： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

    发明人： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

    IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T11/20 ,  G06T17/00 ,  G09G5/02 ,  G09G5/36 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G06F15/20 ,  G06F3/153

    CPC分类号： G06T17/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/203 ,  G09G5/36

    摘要： Herein disclosed is a graphic processing apparatus which uses a CRT of raster scanning type. The graphic processing apparatus has functions to compare and judge whether or not within the range of a predetermined region thereby to effect the drawing operation, to compare drawing picture element data and other data in the drawing operation thereby to arithmetically control the drawing picture element data in accordance with the compared result, and to drawing a pattern of an arbitrary size on the basis of a fundamental unit of line and design patterns in the drawing operation.

    摘要翻译： 这里公开了使用光栅扫描型CRT的图形处理装置。 图形处理装置具有比较判定是否在预定区域的范围内进行绘图操作的功能，以便在绘图操作中比较绘制图像元素数据和其他数据，从而对图形元素数据进行算术控制 根据比较结果，并在绘图操作中基于线和设计图案的基本单位绘制任意尺寸的图案。

    Display controller
    97.
    发明授权
    Display controller 失效
    显示控制器

    公开(公告)号：US4757310A

    公开(公告)日：1988-07-12

    申请号：US626992

    申请日：1984-07-02

    申请人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

    发明人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

    IPC分类号： G06F3/153 ,  G06F3/14 ,  G09G1/02 ,  G09G5/14 ,  G09G5/32 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  G09G5/395 ,  G09G5/397 ,  G09G1/16

    CPC分类号： G09G5/36 ,  G09G5/363 ,  G09G5/39 ,  G09G5/397

    摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.

    摘要翻译： 在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性 通过将单位时钟分割成预定数量以高速功能和多功能显示。 当图像数据要被输入到与显示帧相对应的刷新存储器中时，以1：n的比例分配存储器内容和显示地址以并行地进行处理。 结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示 。 所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

    Microprogram memory with page addressing and address decode in memory
    98.
    发明授权
    Microprogram memory with page addressing and address decode in memory 失效
    存储器中的页面寻址和地址解码的微程序存储器

    公开(公告)号：US4446517A

    公开(公告)日：1984-05-01

    申请号：US269608

    申请日：1981-06-02

    申请人： Koyo Katsura ,  Hideo Maejima

    发明人： Koyo Katsura ,  Hideo Maejima

    IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F11/00 ,  G06F11/28

    CPC分类号： G06F11/0751 ,  G06F11/28 ,  G06F9/223 ,  G06F9/26 ,  G06F9/261 ,  G06F9/265

    摘要： A microprogram control system in which the processing speed of a microprogram is increased and the capacity of the microprogram memory is reduced. The decoder previously provided in microprogram control systems to decode the contents of the instruction register are omitted to attain an increased processing speed and the instruction decoding function is integrated into the microprogram memory to attain a general purpose control system. The microprogram memory is divided into pages each consisting of a plurality of words, so that an arbitrary page can be designated as an instruction decode area under the control of the microprogram. Error checking in the system is facilitated by providing a check function for readout error, and a short word memory device is used to reduce the memory capacity of the microprogram memory.

    摘要翻译： 一种微程序控制系统，其中微程序的处理速度增加并且微程序存储器的容量减小。 先前在微程序控制系统中提供的解码指令寄存器的内容的解码器被省略以获得增加的处理速度，并且指令解码功能被集成到微程序存储器中以实现通用控制系统。 微程序存储器被分成由多个单词组成的页面，使得可以在微程序的控制下将任意页面指定为指令解码区域。 通过提供读出错误的检查功能便于系统中的错误检查，并且使用短字存储器件来减少微程序存储器的存储器容量。