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公开(公告)号：US20120076174A1
公开(公告)日：2012-03-29
申请号：US13309998
申请日：2011-12-02
IPC分类号： H04B1/713
CPC分类号： H04B1/71632 , H04B1/713 , H04L27/2601
摘要： A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.
摘要翻译： 快速跳频收发器包括布置在第一芯片上的RF单元，第二芯片上的基带单元，布置在所述第一芯片和所述第二芯片之间的双向可操作数据和控制接口，其具有用于数据的至少一条数据线 通信，用于控制数据通信的至少一个控制线和用于提供时钟信号的至少一个时钟线;在所述RF单元内实现的存储装置，其包含特定于接收到的某个频率的所有所需的芯片设置和/或 传输数据是预期跳频序列的一部分。 收发器还包括用于在建立所述数据通信的通信链路期间的初始化阶段期间对所述存储器装置进行编程的控制装置。
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公开(公告)号：US08134396B2
公开(公告)日：2012-03-13
申请号：US12392046
申请日：2009-02-24
IPC分类号： H03H11/26
CPC分类号： H03M1/066 , G04F10/005 , H03M1/502
摘要： This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.
摘要翻译： 本公开涉及延迟线电路中的动态元件匹配以减少线性劣化和延迟线不匹配。
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公开(公告)号：US08094752B2
公开(公告)日：2012-01-10
申请号：US11118622
申请日：2005-04-29
申请人： Martin Friedrich , Christian Grewing , Giuseppe Li Puma , Christoph Sandner , Andreas Wiesbauer , Kay Winterberg , Stefan Van Waasen
发明人： Martin Friedrich , Christian Grewing , Giuseppe Li Puma , Christoph Sandner , Andreas Wiesbauer , Kay Winterberg , Stefan Van Waasen
IPC分类号： H04L25/06
CPC分类号： H04B1/69
摘要： Amplifier for an ultra-wideband (UWB) signal receiver having a signal input (15) for receiving an ultra-wideband signal which is sent by a transmitter (1) and which is transmitted in a sequence of transmission channels (Ki) (which each have a particular frequency bandwidth) which has been agreed between the transmitter (1) and the receiver (4); a transistor (18) whose control connection is connected to the signal input (15); a resonant circuit (26, 30, 31) which is connected to the transistor (18) and whose resonant frequency can be set for the purpose of selecting the transmission channel (Ki) in line with the agreed sequence of transmission channels; and having a signal output (29) for outputting the amplified ultra-wideband signal, the signal output being tapped off between the transistor (18) and the resonant circuit.
摘要翻译： 一种用于超宽带（UWB）信号接收机的放大器，具有用于接收由发射机（1）发送并且以传输信道（Ki）序列（Ki）发送的超宽带信号的信号输入（15） 具有特定的频率带宽），其在发射机（1）和接收机（4）之间已被约定; 控制连接到信号输入端（15）的晶体管（18）; 连接到晶体管（18）并且其谐振频率可以被设置为用于根据所约定的传输信道序列选择传输信道（Ki）的谐振电路（26,30,31）; 并且具有用于输出放大的超宽带信号的信号输出（29），所述信号输出在所述晶体管（18）和所述谐振电路之间被分接。
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公开(公告)号：US08090001B2
公开(公告)日：2012-01-03
申请号：US11294213
申请日：2005-12-05
IPC分类号： H04B1/713
CPC分类号： H04B1/71632 , H04B1/713 , H04L27/2601
摘要： A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.
摘要翻译： 快速跳频收发器包括布置在第一芯片上的RF单元，第二芯片上的基带单元，布置在所述第一芯片和所述第二芯片之间的双向可操作数据和控制接口，其具有用于数据的至少一条数据线 通信，用于控制数据通信的至少一个控制线和用于提供时钟信号的至少一个时钟线;在所述RF单元内实现的存储装置，其包含特定于接收到的某个频率的所有所需的芯片设置和/或 传输数据是预期跳频序列的一部分。 收发器还包括用于在建立所述数据通信的通信链路期间的初始化阶段期间对所述存储器装置进行编程的控制装置。
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公开(公告)号：US08064856B2
公开(公告)日：2011-11-22
申请号：US12111654
申请日：2008-04-29
申请人： Peter Singerl , Andreas Wiesbauer
发明人： Peter Singerl , Andreas Wiesbauer
CPC分类号： H04B1/0475 , H03F1/02 , H03F3/24 , H04B2001/045
摘要： A power amplifier includes a baseband modulator configured to receive a baseband amplitude component and generate a baseband modulated pulse string, an oscillator configured to receive a baseband phase component and generate phase modulated complex carrier signals, a complex up-converter configured to receive and mix the baseband modulated pulse string with the phase modulated complex carrier signals into mixed product signals, and two or more switched mode power amplifiers coupled to the complex up-converter, configured to amplify and switch the mixed product signals at the carrier frequency. The power amplifier further comprises complex filters individually coupled to one of the switch mode power amplifiers, configured to suppress image components in the amplified and switched mixed product signals, and a power combiner coupled to the two or more complex filters, configured to combine the real component of the complex filtered and amplified mixed product signals to generate an RF transmission signal.
摘要翻译： 功率放大器包括：基带调制器，被配置为接收基带振幅分量并产生基带调制脉冲串;振荡器，被配置为接收基带相位分量并产生相位调制的复数载波信号;复合上变频器，被配置为接收和混合 具有相位调制复载波信号的基带调制脉冲串到混合乘积信号中，并且耦合到复合上变频器的两个或更多个开关模式功率放大器被配置为在载波频率处放大和切换混合乘积信号。 功率放大器还包括单独耦合到开关模式功率放大器之一的复合滤波器，其被配置为抑制放大和切换的混合乘积信号中的图像分量，以及耦合到两个或更多个复杂滤波器的功率组合器，被配置为组合真实的 复合滤波和放大的混合乘积信号的分量以产生RF传输信号。
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97.发明授权Asynchronous sigma delta analog to digital converter using a time to digital converter 有权异步Σ-Δ模数转换器采用时间到数字转换器公开(公告)号：US07859442B2
公开(公告)日：2010-12-28
申请号：US12245221
申请日：2008-10-03
申请人： Jorg Daniels , Wim Dehaene , Andreas Wiesbauer
发明人： Jorg Daniels , Wim Dehaene , Andreas Wiesbauer
IPC分类号： H03M3/00
CPC分类号： H03M1/1265 , G04F10/005 , H03M3/43 , H03M3/432 , H03M3/456 , H03M3/498
摘要： This disclosure relates to analog to digital conversion using irregular sampling.
摘要翻译： 本公开涉及使用不规则采样的模数转换。
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公开(公告)号：US07834789B2
公开(公告)日：2010-11-16
申请号：US12418632
申请日：2009-04-06
IPC分类号： H03M3/00
摘要： Techniques for reducing sampling error in electronic components are described herein.
摘要翻译： 本文描述了用于减少电子部件中的采样误差的技术。
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99.发明授权公开(公告)号：US07643802B2
公开(公告)日：2010-01-05
申请号：US11492466
申请日：2006-07-25
申请人： Stefano Marsili , Andreas Wiesbauer , Marc Tiebout
发明人： Stefano Marsili , Andreas Wiesbauer , Marc Tiebout
IPC分类号： H04B1/04
CPC分类号： H04B1/525
摘要： A mixer circuit includes a first oscillator, a second oscillator, an up-conversion mixer, a down-conversion mixer, and a detect and control unit. The up-conversion mixer has a first input terminal coupled to the first oscillator and an output terminal. The down-conversion mixer has a first input terminal coupled to the output terminal of the up-conversion mixer and a second input terminal coupled to the second oscillator. The detect and control unit is coupled to the down-conversion mixer.
摘要翻译： 混频器电路包括第一振荡器，第二振荡器，上变频混频器，下变频混频器以及检测和控制单元。 上变换混频器具有耦合到第一振荡器的第一输入端和输出端。 下转换混频器具有耦合到上转换混频器的输出端的第一输入端和耦合到第二振荡器的第二输入端。 检测和控制单元耦合到下变频混频器。
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公开(公告)号：US07633419B2
公开(公告)日：2009-12-15
申请号：US12032248
申请日：2008-02-15
IPC分类号： H03M3/00
摘要： Techniques for converting signals using finite impulse response (FIR) feedback are described herein.
摘要翻译： 本文描述了使用有限脉冲响应（FIR）反馈来转换信号的技术。
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