公开(公告)号：US07362193B2

公开(公告)日：2008-04-22

申请号：US10526244

申请日：2003-08-14

申请人： Sven Mattisson

发明人： Sven Mattisson

IPC分类号： H03B5/36

CPC分类号： H03B5/364 ,  H03B5/36

摘要： A balanced crystal oscillator circuit comprising: a piezoelectric element Xtal (207; 215; 222,221; 313); a first oscillator subcircuit (202; 210; 218; 302) incorporating a transistor (204;212;220;304); and a second oscillator subcircuit (201;209;217; 301) incorporating a transistor (203; 211; 219; 303); wherein the transistors each have different types of transistor terminals (C,B,E; D;G;S), and wherein the oscillator subcircuits are configured with at least three interconnections. Each interconnection comprise a pair of like type of transistor terminals; wherein a first of said interconnections constitutes a connection to a ground reference (gnd); a second of said interconnections is via a first resonator element (207;215;223;313); and a third of said interconnections is via a second resonator element (208;216;224;314); said first and second circuits are arranged to interact by means of said first and second resonator elements to form a balanced oscillator signal. A dual common base or a dual common collector configuration is preferred.

摘要翻译： 一种平衡晶体振荡器电路，包括：压电元件Xtal（207; 215; 222,221; 313）; 包括晶体管（204; 212; 220; 304）的第一振荡器子电路（202; 210; 218; 302） 以及并入有晶体管（203; 211; 219; 303）的第二振荡器子电路（201; 209; 217; 301） 其中所述晶体管各自具有不同类型的晶体管端子（C，B，E; D; G; S），并且其中所述振荡器子电路配置有至少三个互连。 每个互连包括一对类似的晶体管端子; 其中所述互连中的第一个构成与地面参考（gnd）的连接; 所述互连中的第二个是经由第一谐振器元件（207; 215; 223; 313）; 并且所述互连中的三分之一经由第二谐振器元件（208; 216; 224; 314）; 所述第一和第二电路被布置成通过所述第一和第二谐振器元件相互作用以形成平衡振荡器信号。 双重共用基底或双共同收集器配置是优选的。

公开(公告)号：US07068171B2

公开(公告)日：2006-06-27

申请号：US10822594

申请日：2004-04-12

申请人： Karl Håkan Torbjörn Gärdenfors ,  Sven Mattisson ,  Jacobus Cornelis Haartsen

发明人： Karl Håkan Torbjörn Gärdenfors ,  Sven Mattisson ,  Jacobus Cornelis Haartsen

IPC分类号： H04Q1/00

CPC分类号： H04B1/44 ,  H04B1/3833 ,  H04B1/408 ,  H04B1/715 ,  H04B15/00 ,  H04B2001/7152 ,  H04J3/10 ,  H04L5/1461 ,  H04L27/122

摘要： An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

公开(公告)号：US07054609B2

公开(公告)日：2006-05-30

申请号：US10400114

申请日：2003-03-26

申请人： Magnus Wiklund ,  Sven Mattisson

发明人： Magnus Wiklund ,  Sven Mattisson

IPC分类号： H04B1/26 ,  H04B1/28

CPC分类号： H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1491

摘要： Method and system are disclosed for providing an improved linearity Gilbert mixer. The Gilbert mixer of the present invention includes a conventional mixer core coupled to a high linearity, multistage amplifier. The multistage amplifier includes two or more transistor stages connected together in a global feedback arrangement. The global feedback provides a greater loop gain for the amplifier than the local feedback arrangement, thereby increasing the linearity of the amplifier. In addition, having more than one transistor stage in the amplifier serves to increase the isolation of the RF input signal from the LO input signal. Furthermore, by providing parallel output stages in the multistage amplifier, several mixer cores may be driven from the same source while sharing the feedback mechanism.

公开(公告)号：US20060079194A1

公开(公告)日：2006-04-13

申请号：US11274446

申请日：2005-11-15

申请人： Tobias Tired ,  Sven Mattisson

发明人： Tobias Tired ,  Sven Mattisson

IPC分类号： H04B1/06 ,  H04B1/10 ,  H04B1/26

CPC分类号： H04B1/109 ,  H03D7/145 ,  H03D7/165 ,  H03D2200/0025 ,  H03F3/191 ,  H03F3/50 ,  H03F2200/294 ,  H03J2200/10

摘要： A radiofrequency (RF) receiver circuit and method offer one or more performance improvements, such as an increased input compression point through better out-of-band interference suppression. In one example, an RF receiver circuit includes a low-noise amplifier (LNA) circuit and a mixer. The mixer output signal serves as negative feedback to the LNA circuit for improved compression point performance at interferer frequencies in or out of band with respect to a frequency of interest. Compression point performance is further improved for interferer signal components away from the frequency of interest by including at least one frequency-dependent circuit in the LNA circuit that is configured to reduce amplifier gain for such frequencies. The frequency-dependent circuit(s) may be tunable for different frequencies of interest. Additional improvements may be obtained by including a broadband input matching circuit and/or by including active mixer loads to increase the voltage conversion gain of the RF receiver circuit.

摘要翻译： 射频（RF）接收机电路和方法提供一个或多个性能改进，例如通过更好的带外干扰抑制来增加输入压缩点。 在一个示例中，RF接收器电路包括低噪声放大器（LNA）电路和混频器。 混频器输出信号用作对LNA电路的负反馈，以改善关于感兴趣频率的频带内或频带内的干扰频率的压缩点性能。 通过在LNA电路中包括至少一个与频率相关的频率相关电路来配置，以减少这种频率的放大器增益，来进一步提高干扰信号分量远离感兴趣频率的压缩点性能。 对于感兴趣的不同频率，频率相关电路可以是可调谐的。 可以通过包括宽带输入匹配电路和/或通过包括有源混频器负载来增加RF接收器电路的电压转换增益来获得额外的改进。

公开(公告)号：US20050248416A1

公开(公告)日：2005-11-10

申请号：US10837573

申请日：2004-05-04

申请人： Sven Mattisson ,  Hans Hagberg

发明人： Sven Mattisson ,  Hans Hagberg

IPC分类号： H03B1/00 ,  H03B5/04

CPC分类号： H03B5/04

摘要： Disclosed are methods and circuit configurations for reference frequency signal distribution circuitry that suppress unwanted spurious components introduced by way of RF signal leakage. The methods and circuitry may include relocating components of a buffer along a reference frequency signal path, thereby suppressing conductive and inductive components associated with RF leakage paths entering the circuitry. A filter also may be used after the buffer to suppress spurious components resulting from subsampling of unwanted tones in a phase frequency detector or intermodulation between the reference signal and interference tones in the signal-path of the buffer.

摘要翻译： 公开了用于抑制通过RF信号泄漏引入的不想要的杂散分量的参考频率信号分配电路的方法和电路配置。 方法和电路可以包括沿着参考频率信号路径重新定位缓冲器的部件，从而抑制与进入电路的RF泄漏路径相关联的导电和感应部件。 也可以在缓冲器之后使用滤波器来抑制由相位频率检测器中的不想要的音调的二次采样引起的杂散分量或者在缓冲器的信号路径中的参考信号和干扰音调之间的互调。

公开(公告)号：US06734749B2

公开(公告)日：2004-05-11

申请号：US09867921

申请日：2001-05-29

申请人： Sven Mattisson ,  Håkan Eriksson

发明人： Sven Mattisson ,  Håkan Eriksson

IPC分类号： H03C300

CPC分类号： H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095

摘要： Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

摘要翻译： 通过包括数字序列的调制信号来实现锁相环（PLL）输出信号的直接频率调制。 数字调制信号耦合到PLL的VCO的输入，并且还耦合以驱动上下计数器。 计数器的输出耦合到D / A转换器，为PLL提供补偿信号。 当计数器输出达到表示+ 360度和-360度的调制诱发相位误差的值时，计数器产生分别对应的信号以调整PLL分频器。

公开(公告)号：US06633550B1

公开(公告)日：2003-10-14

申请号：US08803392

申请日：1997-02-20

申请人： Karl Håkan Torbjörn Johansson Gärdenfors ,  Sven Mattisson ,  Jacobus Cornelis Haartsen

发明人： Karl Håkan Torbjörn Johansson Gärdenfors ,  Sven Mattisson ,  Jacobus Cornelis Haartsen

IPC分类号： H04B7005

CPC分类号： H04B1/44 ,  H04B1/3833 ,  H04B1/408 ,  H04B1/715 ,  H04B15/00 ,  H04B2001/7152 ,  H04J3/10 ,  H04L5/1461 ,  H04L27/122

摘要： An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

摘要翻译： 整个无线电收发器可以完全集成到一个IC芯片中。 为了在芯片上集成IF滤波器，使用具有低IF的外差架构。 单个直接调制的VCO用于传输期间的上转换和接收期间的下变频。 在VCO的振荡器槽中使用接合线作为谐振器。 在空中接口中使用TDD方案来消除串扰或泄漏。 高斯形二进制FSK调制方案用于提供许多其他实现优点。

公开(公告)号：US06404308B1

公开(公告)日：2002-06-11

申请号：US09472363

申请日：1999-12-23

申请人： Sven Mattisson

发明人： Sven Mattisson

IPC分类号： H03H1142

CPC分类号： H03H11/42

摘要： Integrated circuits, for example, gyrator circuits include transistors that are preferably MOS devices and that are provided with series feedback networks, which compensate for the effects of channel delay in the MOS devices.

摘要翻译： 集成电路，例如，回转器电路包括优选MOS器件并且具有串联反馈网络的晶体管，其补偿MOS器件中的沟道延迟的影响。

公开(公告)号：US06373909B1

公开(公告)日：2002-04-16

申请号：US09426782

申请日：1999-10-22

申请人： Björn Lindquist ,  Jan Celander ,  Sven Mattisson

发明人： Björn Lindquist ,  Jan Celander ,  Sven Mattisson

IPC分类号： H03D104

摘要： A communications terminal having a receiver and a method therefor is provided that substantially removes a known interferer from a digitally translated intermediate frequency signal. More specifically, the receiver includes an antenna for receiving a signal, and at least one combination of a mixer and filter for translating in the analog domain the signal to the intermediate frequency signal while maintaining separation from baseband. The receiver also includes a digitizer for digitally translating the intermediate frequency signal containing the known interferer from the analog domain into the digital domain, and an interference cancellation system for removing the known interferer from the digitally translated intermediate frequency signal by utilizing either a DC offset compensator or a correlator compensator.

公开(公告)号：US6104238A

公开(公告)日：2000-08-15

申请号：US274331

申请日：1999-03-23

申请人： Sven Mattisson ,  Jacobus Haartsen

发明人： Sven Mattisson ,  Jacobus Haartsen

IPC分类号： H03D3/00 ,  H04L27/152 ,  H04L27/14

CPC分类号： H03D3/005 ,  H04L27/152

摘要： An FM demodulator circuit includes a filter (10) and a detector (14) for receiving a frequency modulated input signal and for providing a demodulated output signal. A tuning circuit (19) is provided for tuning the frequency characteristics of the filter and of the detector. A DC offset estimator (18) is connected to the output of the detector to produce an offset signal representing the estimated DC offset of the demodulated output signal, and to provide the offset signal to the tuning circuit. The tuning circuit is operable to tune the frequency characteristics of the filter and detector in dependence upon the offset signal.

摘要翻译： FM解调器电路包括用于接收调频输入信号并提供解调输出信号的滤波器（10）和检测器（14）。 提供调谐电路（19），用于调谐滤波器和检测器的频率特性。 DC偏移估计器（18）连接到检测器的输出，以产生表示经解调的输出信号的估计的DC偏移的偏移信号，并将偏移信号提供给调谐电路。 调谐电路可操作以根据偏移信号来调谐滤波器和检测器的频率特性。