公开(公告)号：US12178038B2

公开(公告)日：2024-12-24

申请号：US17141873

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

IPC: H10B12/00 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a CMOS-containing base containing wordline-driver-circuitry. The wordline-driver-circuitry is subdivided amongst horizontally-extending sub-wordline-driver (SWD) units. Memory cells are over the base, and are arranged in vertically-extending rows. Each of the memory cells includes an access device and a storage element coupled with the access device. Wordlines extend vertically along the rows. Each of the SWD units is associated with at least two of the wordlines and is configured to simultaneously activate the associated wordlines.

公开(公告)号：US12176020B2

公开(公告)日：2024-12-24

申请号：US17821645

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

IPC: G11C8/14 ,  G11C5/02 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06 ,  G11C11/401

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

公开(公告)号：US20240363241A1

公开(公告)日：2024-10-31

申请号：US18764929

申请日：2024-07-05

Applicant: Micron Technology, Inc.

Inventor： Gitanjali T. Ghosh ,  Irene K. Thompson ,  Jessica M. Maderos ,  Hongmei Wang ,  Fatma Arzum Simsek-Ege ,  Kathryn H. Russo

IPC: G16H40/67 ,  G16H10/60 ,  G16H40/63 ,  G16H80/00

CPC classification number: G16H40/67 ,  G16H10/60 ,  G16H40/63 ,  G16H80/00

Abstract: Systems, apparatuses, and methods related to medical device data analysis are described. In some examples, a medical device is implanted in a user of the medical device and the data generated by the medical device is not easily accessible to the user. In an example, a controller can be configured to receive, by a mobile device coupled to a medical device, data from the medical device, where the data is a part of a baseline dataset related to the medical device. The controller can be configured to receive different data from the medical device, where the different data is received from the medical device as the different data is generated by the medical device, analyze the data from the medical device and the different data generated by the medical device, and perform an action based on the analyzed data and the different data generated by the medical device.

公开(公告)号：US12131794B2

公开(公告)日：2024-10-29

申请号：US17893681

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H10B12/00

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H10B12/488

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

公开(公告)号：US12113052B2

公开(公告)日：2024-10-08

申请号：US18491678

申请日：2023-10-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/528 ,  H01L23/53228 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2225/06541

Abstract: A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures.

公开(公告)号：US20240172425A1

公开(公告)日：2024-05-23

申请号：US18429004

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H10B12/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H10B12/485 ,  H01L25/0657 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50 ,  H10B80/00

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11925031B2

公开(公告)日：2024-03-05

申请号：US17950968

申请日：2022-09-22

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B53/30 ,  H01L21/768 ,  H01L49/02 ,  H10B12/00 ,  H10B53/10

CPC classification number: H10B53/30 ,  H01L21/7688 ,  H01L28/60 ,  H10B12/0335 ,  H10B53/10

Abstract: A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group.

公开(公告)号：US11924730B2

公开(公告)日：2024-03-05

申请号：US17101761

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Anshika Sharma ,  Deepti Verma ,  Fatma Arzum Simsek-Ege ,  Trupti D. Gawai ,  Lavanya Sriram

IPC: H04W4/90 ,  B64C39/02 ,  G01V1/00 ,  G08B7/06 ,  H04W4/021 ,  H04W76/50

CPC classification number: H04W4/90 ,  B64C39/024 ,  G01V1/008 ,  G08B7/066 ,  H04W4/022 ,  H04W76/50

Abstract: Methods, systems, and devices for operating emergency prevention sensor systems are described. Devices can include a plurality of components including a sensor component, a processor, and memory. In an example, a method can include receiving at a processor signaling from a plurality of environmental sensing devices, each having at least one biodegradable component, in an area of concern, wherein the area of concern corresponds to a particular set of coordinates in a database, determining environmental characteristics of an emergency associated with the area of concern based, at least in part, on the signaling, and determining a preventive action based on the determined characteristics. In another example, a number of components of the sensing devices are biodegradable.

公开(公告)号：US20240071467A1

公开(公告)日：2024-02-29

申请号：US17893654

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  H10B80/00

CPC classification number: G11C11/4085 ,  G11C11/4087 ,  H10B80/00

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US20240047428A1

公开(公告)日：2024-02-08

申请号：US18491678

申请日：2023-10-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/528 ,  H01L23/53228 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2224/08145

Abstract: A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures.