中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

125 records (took 0.028 seconds)

    Accessing status information
    91.
    发明授权
    Accessing status information 有权

    公开(公告)号：US10725952B2

    公开(公告)日：2020-07-28

    申请号：US16415841

    申请日：2019-05-17

    Applicant: Micron Technology, Inc.

    Inventor： Debra M. Bell

    IPC: G06F13/16 ,  G06F13/366 ,  G11C7/00 ,  G06F11/00 ,  G11C7/24 ,  G06F13/24 ,  G06F13/28

    Abstract: The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. The memory device includes a controller configured to provide, to a status arbiter, a status signal indicating whether a status register of the controller contains generated status information. Responsive to the status signal indicating that the status register contains the generated status information, the controller can also provide the status information from the controller to the status arbiter via a status intermediary.

    PHASE CHARGE SHARING REDUCTION
    92.
    发明申请
    PHASE CHARGE SHARING REDUCTION 审中-公开

    公开(公告)号：US20200185024A1

    公开(公告)日：2020-06-11

    申请号：US16216894

    申请日：2018-12-11

    Applicant: Micron Technology, Inc.

    Inventor： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

    IPC: G11C11/4094 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/408

    Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

    Memory cells and memory arrays
    93.
    发明授权
    Memory cells and memory arrays 有权

    公开(公告)号：US10468421B2

    公开(公告)日：2019-11-05

    申请号：US16204409

    申请日：2018-11-29

    Applicant: Micron Technology Inc.

    Inventor： Debra M. Bell ,  Scott J. Derner

    IPC: G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  H01L27/02 ,  H01L27/06 ,  G11C11/419

    Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

    APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES
    95.
    发明申请
    APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES 审中-公开

    公开(公告)号：US20190130961A1

    公开(公告)日：2019-05-02

    申请号：US16231327

    申请日：2018-12-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

    IPC: G11C11/406 ,  G11C7/10

    Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may he configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

    Memory cells and memory arrays
    96.
    发明授权
    Memory cells and memory arrays 有权

    公开(公告)号：US10177159B2

    公开(公告)日：2019-01-08

    申请号：US15796611

    申请日：2017-10-27

    Applicant: Micron Technology, Inc.

    Inventor： Debra M. Bell ,  Scott J. Derner

    IPC: G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G11C11/419

    Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

    Memory device sensors
    97.
    发明授权
    Memory device sensors 有权

    公开(公告)号：US12298835B2

    公开(公告)日：2025-05-13

    申请号：US18379440

    申请日：2023-10-12

    Applicant: Micron Technology, Inc.

    Inventor： Debra M. Bell ,  Roya Baghi ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Cheryl M. O'Donnell

    IPC: G06F1/3234 ,  G11C11/56 ,  G11C16/26

    Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

    USING MEMORY DEVICE SENSORS
    98.
    发明申请
    USING MEMORY DEVICE SENSORS 有权

    公开(公告)号：US20240411655A1

    公开(公告)日：2024-12-12

    申请号：US18808825

    申请日：2024-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Cheryl M. O'Donnell ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Debra M. Bell ,  Roya Baghi

    IPC: G06F11/30 ,  B60H1/00 ,  G06F11/32 ,  G06F13/16

    Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, another device can be coupled to a memory device with an embedded sensor. The memory device can transmit a signal representing sensor data generated by the embedded sensor using a sensor output coupled to the other device. A controller coupled to a memory device may determine one or more threshold values of a sensor or sensors embedded in a memory device. The memory device may transmit an indication responsive to one or more sensors detecting a value greater or less than a threshold and may transmit the indication to another device.

Patent Agency Ranking