公开(公告)号：US11107515B2

公开(公告)日：2021-08-31

申请号：US16937402

申请日：2020-07-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11507 ,  H01L27/11514 ,  H01L49/02 ,  H01L27/11502

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US20210143142A1

公开(公告)日：2021-05-13

申请号：US17125651

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Charles L. Ingalls ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Scott J. Derner

IPC: H01L25/18 ,  G11C11/408 ,  H01L27/108 ,  G11C11/4091 ,  H01L23/528

Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

公开(公告)号：US20210125661A1

公开(公告)日：2021-04-29

申请号：US17140540

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/4097 ,  H01L27/108 ,  G11C11/4091 ,  H01L27/12

Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

公开(公告)号：US10957681B1

公开(公告)日：2021-03-23

申请号：US16553448

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Charles L. Ingalls ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Scott J. Derner

IPC: G11C11/40 ,  H01L25/18 ,  G11C11/4091 ,  H01L23/528 ,  H01L27/108 ,  G11C11/408 ,  H01L29/78

Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

公开(公告)号：US10957382B2

公开(公告)日：2021-03-23

申请号：US16408095

申请日：2019-05-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/408

Abstract: Some embodiments include an integrated assembly having a base with sense-amplifier-circuitry. A first deck is over the base, and includes a first array of first memory cells. A second deck over the first deck, and includes a second array of second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

公开(公告)号：US10854617B2

公开(公告)日：2020-12-01

申请号：US16379365

申请日：2019-04-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L Ingalls

IPC: H01L27/11507 ,  H01L29/78 ,  H01L23/528 ,  H01L27/11514 ,  H01L27/108 ,  H01L29/08 ,  H01L27/02 ,  H01L49/02

Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

公开(公告)号：US10818342B2

公开(公告)日：2020-10-27

申请号：US16105631

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4091 ,  G11C7/06 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108 ,  G11C5/02 ,  G11C7/18 ,  G11C8/16 ,  G11C11/4096

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US10811083B2

公开(公告)日：2020-10-20

申请号：US16404525

申请日：2019-05-06

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/406

Abstract: Some embodiments include an integrated assembly having a first memory array which includes a first column of first memory cells. A first digit line extends along the first column and is utilized to address the first memory cells of the first column. A second memory array is proximate to the first memory array and includes a second column of second memory cells. A second digit line extends along the second column and is utilized to address the second memory cells of the second column. A primary-sense-amplifier comparatively couples the first digit line with the second digit line. A first secondary-sense-amplifier is along the first digit line, and a second secondary-sense-amplifier is along the second digit line.

公开(公告)号：US10726907B2

公开(公告)日：2020-07-28

申请号：US16125326

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/56

Abstract: An electronic device includes: a memory cell configured to store electric charge for representing a data value, wherein the memory cell is configured to store two or more levels of the electric charge corresponding to different data values; a preamplifier operably coupled to the memory cell, the preamplifier having a common source and configured to generate an amplified signal based on amplifying a difference in the two or more levels of the stored electric charge; and a sense amplifier operably coupled to the preamplifier, the sense amplifier configured to further process the amplified signal for determining the data value stored in the memory cell.

公开(公告)号：US10607994B2

公开(公告)日：2020-03-31

申请号：US16183528

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore

IPC: H01L27/108 ,  G11C11/403 ,  H01L27/07 ,  H01L49/02 ,  H01L29/78 ,  G11C7/18 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.