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113 条记录 (耗时 0.033 秒)

    SOI input protection circuit
    92.
    发明授权
    SOI input protection circuit 失效
    SOI输入保护电路

    公开(公告)号：US6046476A

    公开(公告)日：2000-04-04

    申请号：US559264

    申请日：1995-11-15

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/762 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/861 ,  H01L29/866

    CPC分类号： H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002

    摘要： In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.

    摘要翻译： 在具有SOI结构的输入保护电路中，用于保护MOSFET免受诸如静电的高电压引起的断开，在SOI衬底中提供沟槽以垂直地穿过硅层和掩埋氧化物膜并到达内部 P型硅衬底。 n +多晶硅层埋在沟槽中，通过P-N结与硅衬底连接。 导线连接到n +多晶硅层。 电线的一端连接到输入焊盘，另一端连接到内部电路。 输入电压受到在n +多晶硅层和P型硅衬底之间的界面处的P-N结处的雪崩击穿的限制。

    Semiconductor device
    94.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08014224B2

    公开(公告)日：2011-09-06

    申请号：US12201024

    申请日：2008-08-29

    申请人： Kenji Yoshinaga ,  Fukashi Morishita

    发明人： Kenji Yoshinaga ,  Fukashi Morishita

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

    摘要翻译： 提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。 控制电路，行/列解码器和读出放大器由内部降压电压驱动。 另一方面，具有高功耗的数据路径由外部电源电压驱动。 电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。 电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据路径。

    SOLID-STATE IMAGE PICKUP DEVICE
    95.
    发明申请
    SOLID-STATE IMAGE PICKUP DEVICE 有权
    固态图像拾取器件

    公开(公告)号：US20100231768A1

    公开(公告)日：2010-09-16

    申请号：US12722121

    申请日：2010-03-11

    申请人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

    发明人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

    IPC分类号： H04N5/335

    CPC分类号： H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

    摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

    摘要翻译： 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    96.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路设备

    公开(公告)号：US20100188120A1

    公开(公告)日：2010-07-29

    申请号：US12677745

    申请日：2008-09-19

    申请人： Fukashi Morishita

    发明人： Fukashi Morishita

    IPC分类号： H03K19/0944

    CPC分类号： H01L27/1203 ,  H01L27/088 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/78615

    摘要： The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.

    摘要翻译： 本发明提供一种半导体集成电路器件，其中SOI晶体管的特性被有效地用于实现更高的速度，更高的集成度，并且还降低了电压和功耗。 根据本发明的半导体集成电路器件具有这样的结构，其中多个外部电源线和体电压控制线在一个方向上交替布置，以便在整个芯片上延伸，从而将电源和体电压提供给 逻辑电路，模拟电路和存储器电路。 体电压控制型逻辑门完全应用在逻辑电路中，而体电压控制型逻辑门部分地应用于存储器电路中。

    SEMICONDUCTOR MEMORY DEVICE
    98.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20090022001A1

    公开(公告)日：2009-01-22

    申请号：US12281271

    申请日：2006-03-01

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/405 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.

    摘要翻译： 通过与设置为OFF的存储晶体管并行地激活字线和位线，控制充电线，字线和位线的电位条件，使得身体区域的电位增加一个 在存储晶体管导通的期间内，从连接节点流向身体区域的漏电流。

    Semiconductor Memory Device
    99.
    发明申请
    Semiconductor Memory Device 有权
    半导体存储器件

    公开(公告)号：US20080251860A1

    公开(公告)日：2008-10-16

    申请号：US10593275

    申请日：2005-06-03

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： H01L27/088

    CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

    摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

    摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

    Semiconductor memory device and manufacturing method of the same
    100.
    发明申请
    Semiconductor memory device and manufacturing method of the same 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20080023743A1

    公开(公告)日：2008-01-31

    申请号：US11905002

    申请日：2007-09-27

    申请人： Masakazu Hirose ,  Fukashi Morishita

    发明人： Masakazu Hirose ,  Fukashi Morishita

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10873 ,  G11C11/404 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0218 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78612

    摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

    摘要翻译： 在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。 更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。 主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。 在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。