公开(公告)号：US07109544B2

公开(公告)日：2006-09-19

申请号：US10777128

申请日：2004-02-13

申请人： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

发明人： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

IPC分类号： H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

摘要翻译： 在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。 晶体管单元的较低源极/漏极区域连接到公共连接板。 晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。 沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。 字线形成栅电极。 在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。 根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。 在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。

公开(公告)号：US20060202250A1

公开(公告)日：2006-09-14

申请号：US11076021

申请日：2005-03-10

申请人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

发明人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

IPC分类号： H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L28/82

摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.

摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。

公开(公告)号：US07034408B1

公开(公告)日：2006-04-25

申请号：US11005045

申请日：2004-12-07

申请人： Till Schloesser

发明人： Till Schloesser

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

摘要： A memory device includes a DRAM memory cell array, which is implemented as a 6 F×F array, and peripheral circuitry. The word lines of the memory cell array are implemented as buried word lines, and, in addition, the bit lines including the bit line contacts are made of a bit line layer stack. The peripheral circuitry includes a peripheral transistor including first and second source/drain regions, a channel connecting the first and the second source/drain regions as well as a peripheral gate electrode for controlling an electrical current of the channel. The peripheral gate electrode is made of a peripheral gate stack including a layer stack which is identical with the bit line stack.

摘要翻译： 存储器件包括被实现为6FxF阵列的DRAM存储单元阵列和外围电路。 存储单元阵列的字线被实现为掩埋字线，并且另外，包括位线触点的位线由位线层堆叠构成。 外围电路包括包括第一和第二源极/漏极区域的外围晶体管，连接第一和第二源极/漏极区域的沟道以及用于控制沟道的电流的外围栅极电极。 外围栅电极由包括与位线堆叠相同的层堆叠的外围栅极堆叠制成。

公开(公告)号：US20060017132A1

公开(公告)日：2006-01-26

申请号：US11167946

申请日：2005-06-28

申请人： Albert Birner ,  Andreas Weber ,  Till Schloesser ,  Joern Luetzen

发明人： Albert Birner ,  Andreas Weber ,  Till Schloesser ,  Joern Luetzen

IPC分类号： H01L29/00

CPC分类号： H01L21/31612 ,  C23C16/345 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02131 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/3141 ,  H01L21/3185

摘要： The present invention relates to a method for producing a dielectric on a semiconductor body having the following steps that are to be performed successively: provision of a semiconductor body, application of a dielectric layer on at least parts of a first surface of the semiconductor body in such a way as at least partly to form an interface between the dielectric layer and the semiconductor body, and thermal annealing of the semiconductor body and the dielectric layer. The method according to the invention is distinguished by the fact that temporally prior to the annealing, for the purpose of improving the saturation and the electrical properties, fluorine-containing particles are introduced into regions of the semiconductor body and/or of the dielectric layer which adjoin the interface. The present invention furthermore relates to a corresponding semiconductor structure.

摘要翻译： 本发明涉及一种在半导体本体上制造电介质的方法，其具有以下步骤：连续进行：提供半导体本体，在半导体本体的第一表面的至少一部分上施加电介质层 这种方式至少部分地形成介电层和半导体本体之间的界面，以及半导体本体和电介质层的热退火。 根据本发明的方法的区别在于，在退火之前的时间上，为了提高饱和度和电性能，将含氟颗粒引入到半导体本体和/或电介质层的区域中，其中 毗邻接口。 本发明还涉及相应的半导体结构。

公开(公告)号：US06930325B2

公开(公告)日：2005-08-16

申请号：US10766902

申请日：2004-01-30

申请人： Bernhard Kowalski ,  Andreas Felber ,  Valentin Rosskopf ,  Juergen Lindolf ,  Till Schloesser ,  Bernd Goebel

发明人： Bernhard Kowalski ,  Andreas Felber ,  Valentin Rosskopf ,  Juergen Lindolf ,  Till Schloesser ,  Bernd Goebel

IPC分类号： G11C29/50 ,  H01L23/58

CPC分类号： G11C29/50016 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/5006

摘要： An integrated circuit arrangement that has an integrated test structure is provided. The integrated circuit arrangement includes a transistor array having vertical FET selection transistors electrically coupled to storage capacitors of an assigned memory cell array, the storage capacitors being formed vertically into the depth of a substrate in deep trenches. The test structure may enable a plurality of vertical FET selection transistors by a conductive electrode material embedded in an extended deep trench. With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.

摘要翻译： 提供了具有集成测试结构的集成电路装置。 集成电路装置包括具有电耦合到分配的存储单元阵列的存储电容器的垂直FET选择晶体管的晶体管阵列，所述存储电容器垂直形成在深沟槽中的衬底的深度。 测试结构可以通过嵌入在延伸的深沟槽中的导电电极材料来实现多个垂直FET选择晶体管。 利用这种测试结构，可以评估不同半导体结处以及集成电路装置的不同部分之间的漏电流和电容的特性值，并且还执行可靠性压力测试。

公开(公告)号：US20050083724A1

公开(公告)日：2005-04-21

申请号：US10898706

申请日：2004-07-23

申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

IPC分类号： G11C11/34 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

公开(公告)号：US20050001257A1

公开(公告)日：2005-01-06

申请号：US10777128

申请日：2004-02-13

申请人： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

发明人： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

摘要翻译： 在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。 晶体管单元的较低源极/漏极区域连接到公共连接板。 晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。 沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。 字线形成栅电极。 在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。 根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。 在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。