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1.发明申请公开(公告)号：US20060202250A1
公开(公告)日：2006-09-14
申请号：US11076021
申请日：2005-03-10
IPC分类号： H01L29/94
CPC分类号： H01L27/10852 , H01L27/0207 , H01L28/82
摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.
摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。
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公开(公告)号：US20060234463A1
公开(公告)日：2006-10-19
申请号：US11399811
申请日：2006-04-07
IPC分类号： H01L21/20 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： H01L28/65 , H01L27/1087 , H01L29/66181
摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。
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公开(公告)号：US07531406B2
公开(公告)日：2009-05-12
申请号：US11399811
申请日：2006-04-07
IPC分类号： H01L21/8234
CPC分类号： H01L28/65 , H01L27/1087 , H01L29/66181
摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。
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公开(公告)号：US20080242097A1
公开(公告)日：2008-10-02
申请号：US11729360
申请日：2007-03-28
申请人： Tim Boescke , Annette Saenger , Stefan Jakschik , Christian Fachmann , Matthias Patz , Alejandro Avellan , Thomas Hecht , Jonas Sundqvist
发明人： Tim Boescke , Annette Saenger , Stefan Jakschik , Christian Fachmann , Matthias Patz , Alejandro Avellan , Thomas Hecht , Jonas Sundqvist
CPC分类号： H01L29/945 , C30B25/04 , H01L21/02148 , H01L21/02159 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/31612 , H01L21/31616 , H01L21/31645
摘要： The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.
摘要翻译： 本发明涉及选择性沉积方法。 提供了包括至少一个结构化表面的衬底。 结构化表面包括第一区域和第二区域。 对于第一沉积技术的反应物，第一区域被选择性地钝化，并且第二区域被激活关于第一沉积技术的反应物。 通过第一沉积技术沉积第二区域上的钝化层。 对于选自一组氧化反应物的前体，钝化层是惰性的。 使用第二原子层沉积技术将层沉积在第二区域中，作为使用从氧化反应物组中选择的前体的第二沉积技术。
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公开(公告)号：US20060275981A1
公开(公告)日：2006-12-07
申请号：US11442602
申请日：2006-05-30
申请人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
发明人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/10867
摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.
摘要翻译： 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。
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6.发明授权Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices 有权阻挡层以及在制造半导体器件期间抑制扩散过程的方法公开(公告)号：US07157371B2
公开(公告)日：2007-01-02
申请号：US10653599
申请日：2003-09-02
申请人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
发明人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
IPC分类号： H01L21/44
CPC分类号： H01L27/11502 , H01L21/02178 , H01L21/02181 , H01L21/28061 , H01L21/31138 , H01L21/31604 , H01L21/3162 , H01L21/76802 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11507 , H01L28/57 , H01L29/0895 , H01L29/4941
摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.
摘要翻译： 由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。 该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除 临时阻隔层。
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公开(公告)号：US20070141850A1
公开(公告)日：2007-06-21
申请号：US11565227
申请日：2006-11-30
IPC分类号： C03C15/00 , H01L21/302 , B44C1/22
CPC分类号： H01L21/31111 , C09K13/08
摘要： A semiconductor product includes an exposed Hafnium-containing layer. The Hafnium-containing layer is treated with a solution that includes a low ionic strength organic substance.
摘要翻译： 半导体产品包括暴露的含铪层。 含铪层用包含低离子强度有机物质的溶液处理。
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8.发明申请Solution for wet treatment of hafnium containing materials, use of the solution and a wet treatment process 审中-公开用于湿处理含铪材料的溶液，使用溶液和湿处理工艺公开(公告)号：US20070012662A1
公开(公告)日：2007-01-18
申请号：US11184060
申请日：2005-07-18
IPC分类号： C09K13/00 , C09K13/08 , B44C1/22 , H01L21/461
CPC分类号： H01L21/31111 , C09K13/08
摘要： It is one object to devise a solution which is suitable for a wet treatment of Hafnium containing high-k materials. Furthermore, it is an object to devise a use of this solution in the field of semiconductor device manufacturing. It is also an objective of the invention to devise a process to this aim.
摘要翻译： 一个目的是设计一种适用于湿法处理含有高k材料的铪的溶液。 此外，本发明的目的是在半导体器件制造领域中设计出该解决方案。 本发明的目的还在于为此目的设计一个过程。
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公开(公告)号：US08344438B2
公开(公告)日：2013-01-01
申请号：US12023321
申请日：2008-01-31
IPC分类号： H01L27/108 , H01L29/94 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/65
摘要： The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.
摘要翻译： 本发明涉及包含第一金属层和包含第二金属材料的氮化物，氧化物和氧氮化物中的至少一种的化合物的电极。
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公开(公告)号：US20090194410A1
公开(公告)日：2009-08-06
申请号：US12023321
申请日：2008-01-31
IPC分类号： B23H3/06
CPC分类号： H01L28/65
摘要： The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.
摘要翻译： 本发明涉及包含第一金属层和包含第二金属材料的氮化物，氧化物和氧氮化物中的至少一种的化合物的电极。
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