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    Storage capacitor, array of storage capacitors and memory cell array
    1.
    发明申请
    Storage capacitor, array of storage capacitors and memory cell array 审中-公开
    存储电容器，存储电容器阵列和存储单元阵列

    公开(公告)号：US20060202250A1

    公开(公告)日：2006-09-14

    申请号：US11076021

    申请日：2005-03-10

    申请人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

    发明人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L28/82

    摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.

    摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。

    Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines
    2.
    发明授权
    Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines 有权
    在体积器件中形成的垂直浮体存储晶体管，具有掩埋感和字线

    公开(公告)号：US09484457B2

    公开(公告)日：2016-11-01

    申请号：US13404759

    申请日：2012-02-24

    申请人： Peter Baars ,  Till Schloesser

    发明人： Peter Baars ,  Till Schloesser

    IPC分类号： H01L21/74 ,  H01L29/78 ,  H01L27/108

    CPC分类号： H01L29/7841 ,  H01L27/10802

    摘要： A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.

    摘要翻译： 半导体器件包括存储区域，该存储器区域包括柱状结构形式的浮体晶体管，其以体积结构形式形成。 可以基于掩埋字线和掩埋感测区域或感测线路与适当的位线接触方式组合来适当地寻址支柱结构。

    Method of forming conductive contacts on a semiconductor device with embedded memory and the resulting device
    3.
    发明授权
    Method of forming conductive contacts on a semiconductor device with embedded memory and the resulting device 有权
    在具有嵌入式存储器的半导体器件上形成导电触点的方法以及所得到的器件

    公开(公告)号：US09034753B2

    公开(公告)日：2015-05-19

    申请号：US13164272

    申请日：2011-06-20

    申请人： Till Schloesser ,  Peter Baars

    发明人： Till Schloesser ,  Peter Baars

    IPC分类号： H01L21/4763 ,  H01L27/108 ,  H01L21/768

    CPC分类号： H01L27/10894 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888

    摘要： A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

    摘要翻译： 公开了一种方法，其包括在半导体器件的逻辑区域中形成导电逻辑触点，在半导体器件的存储器阵列中形成位线接触和电容器触点，以及执行至少一个第一公共工艺以形成第一 金属化层包括在逻辑区域中的导电耦合到导电逻辑触点的第一导线和存储器阵列中与导线耦合到位线触点的位线。 所述方法还包括执行至少一个第二公共处理以形成第二金属化层，所述第二金属化层包括导电耦合到所述逻辑区域中的所述第一导电线的第一导电结构和所述存储器阵列中的导电耦合到所述电容器的第二导电结构 联系。

    Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same
    6.
    发明申请
    Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same 有权
    具有与位于非存储器区域中的栅电极相同材料的DRAM位线的半导体器件及其制造方法

    公开(公告)号：US20120280296A1

    公开(公告)日：2012-11-08

    申请号：US13099692

    申请日：2011-05-03

    申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L27/10885

    摘要： Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.

    摘要翻译： 通常，本公开涉及一种具有由与器件的非存储区域中的栅电极相同的材料制成的DRAM位线的半导体器件及其制造方法。 本文公开的一种说明性方法包括形成包括存储器阵列和逻辑区域的半导体器件。 所述方法还包括在所述存储器阵列中形成掩埋字线，并且在形成所述掩埋字线之后，执行第一公共处理操作以形成所述逻辑区域中的导电栅电极的至少一部分并且形成至少一部分 的存储器阵列中的导电位线。

    VERTICAL FLOATING BODY STORAGE TRANSISTORS FORMED IN BULK DEVICES AND HAVING BURIED SENSE AND WORD LINES
    7.
    发明申请
    VERTICAL FLOATING BODY STORAGE TRANSISTORS FORMED IN BULK DEVICES AND HAVING BURIED SENSE AND WORD LINES 有权
    立体式浮体式存储晶体管，形成大容量设备，并具有传感器和字线

    公开(公告)号：US20120217612A1

    公开(公告)日：2012-08-30

    申请号：US13404759

    申请日：2012-02-24

    申请人： Peter Baars ,  Till Schloesser

    发明人： Peter Baars ,  Till Schloesser

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L29/7841 ,  H01L27/10802

    摘要： A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.

    摘要翻译： 半导体器件包括存储区域，该存储器区域包括柱状结构形式的浮体晶体管，其以体积结构形式形成。 可以基于掩埋字线和掩埋感测区域或感测线路与适当的位线接触方式组合来适当地寻址支柱结构。

    Transistor and memory cell array
    8.
    发明授权
    Transistor and memory cell array 有权
    晶体管和存储单元阵列

    公开(公告)号：US07956387B2

    公开(公告)日：2011-06-07

    申请号：US11517558

    申请日：2006-09-08

    申请人： Till Schloesser

    发明人： Till Schloesser

    IPC分类号： H01L26/66 ,  H01L21/02

    CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/11507

    摘要： A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.

    摘要翻译： 形成在具有顶表面的半导体衬底中的晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道以及用于控制在沟道中流动的电流的栅电极。 栅电极设置在限定在半导体衬底的顶表面中的栅极沟槽的下部。 槽的上部填充有绝缘材料。 通道包括脊形状的翅片状部分，其具有垂直于由连接第一和第二源极/漏极区域的线限定的方向的横截面中的顶侧和两个侧面。 栅电极在其顶侧和其两个侧面包围通道。

    Method for fabricating a memory cell arrangement with a folded bit line arrangement and corresponding memory cell arrangement with a folded bit line arrangement
    10.
    发明授权
    Method for fabricating a memory cell arrangement with a folded bit line arrangement and corresponding memory cell arrangement with a folded bit line arrangement 有权
    用于制造具有折叠位线布置的存储单元布置和具有折叠位线布置的相应存储单元布置的方法

    公开(公告)号：US07772631B2

    公开(公告)日：2010-08-10

    申请号：US11493082

    申请日：2006-07-26

    申请人： Till Schloesser

    发明人： Till Schloesser

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10891 ,  H01L27/10852 ,  H01L27/10897

    摘要： An integrated circuit includes a memory cell arrangement with a plurality of active regions along a first direction, a plurality of parallel buried word lines (BWL) along a second direction, a plurality of parallel bitlines along a third direction, and a plurality of storage capacitors. The BWLs run through the active regions. Two of the BWLs are spaced apart from one another and from isolation trenches running through a respective active region, the BWLs being insulated from a channel region by a gate dielectric. The bit lines run perpendicular to the second direction, wherein each bit line makes contact with the relevant source region of the associated active region. The first direction lies between the second and third directions. Storage capacitors are connected to associated drain regions in a respective active region.

    摘要翻译： 集成电路包括具有沿着第一方向的多个有源区的存储单元布置，沿着第二方向的多个并行掩埋字线（BWL），沿着第三方向的多个平行位线，以及多个存储电容器 。 BWL运行在活动区域​​。 BWL中的两个彼此间隔开，并且从穿过相应的有源区域的隔离沟槽间隔开，BWL通过栅极电介质与沟道区域绝缘。 位线垂直于第二方向延伸，其中每个位线与相关联的有源区域的相关源极区域接触。 第一个方向在第二和第三个方向之间。 存储电容器连接到相应的有源区域中的相关联的漏极区域。