公开(公告)号：US08313960B1

公开(公告)日：2012-11-20

申请号：US13371380

申请日：2012-02-10

申请人： Ebrahim Abedifard ,  Parviz Keshtbod

发明人： Ebrahim Abedifard ,  Parviz Keshtbod

IPC分类号： H01L21/00

CPC分类号： H01L43/12

摘要： A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting.

摘要翻译： 一种制造磁存储元件的方法包括以下步骤：在底部电极的顶部形成永久磁性层，在永久磁性层的顶部形成钉扎层，形成包含阻挡层的磁性隧道结（MTJ） 钉扎层，在MTJ的顶部形成顶部电极，在顶部电极的顶部上形成硬掩模，并且使用硬掩模执行一系列蚀刻工艺以将MTJ和顶部电极的宽度减小到基本上 当检测到钉扎层中的预定材料时，这些蚀刻工艺中的一个停止，从而避免金属沉积到蚀刻工艺的阻挡层上，从而防止短路。

公开(公告)号：US08289757B2

公开(公告)日：2012-10-16

申请号：US12778725

申请日：2010-05-12

申请人： Parviz Keshtbod ,  Ebrahim Abedifard

发明人： Parviz Keshtbod ,  Ebrahim Abedifard

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

摘要： A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

摘要翻译： 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US06404246B1

公开(公告)日：2002-06-11

申请号：US09741971

申请日：2000-12-20

申请人： Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

发明人： Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

IPC分类号： H03L706

CPC分类号： H03L7/18 ,  H03K3/0231 ,  H03L7/087

摘要： A system and method of generating an output signal of very precise frequency without the use of a crystal oscillator. An input signal is generated using any convenient such as an RC oscillator. A circuit for producing a frequency-controlled output signal comprises a phase lock loop having a VCO and a down counter. The down counter reduces the frequency of a VCO clock signal in accordance with a down count value. The down count value is loaded in a register and stored in non-volatile memory. The down count value is set during a calibration operation using a precision external clock signal. In this way, a clock signal with a highly precise frequency is generated without using a crystal oscillator.

摘要翻译： 一种在不使用晶体振荡器的情况下产生非常精确频率的输出信号的系统和方法。 使用任何方便的RC振荡器产生输入信号。 用于产生频率控制的输出信号的电路包括具有VCO和向下计数器的锁相环。 下降计数器根据递减计数值降低VCO时钟信号的频率。 递减计数值加载到寄存器中并存储在非易失性存储器中。 在使用精密外部时钟信号的校准操作期间设置递减计数值。 以这种方式，在不使用晶体振荡器的情况下产生具有高精度频率的时钟信号。

公开(公告)号：US4608585A

公开(公告)日：1986-08-26

申请号：US403694

申请日：1982-07-30

申请人： Parviz Keshtbod

发明人： Parviz Keshtbod

IPC分类号： H01L27/112 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/50

CPC分类号： G11C16/0441 ,  H01L29/7883 ,  H01L27/115

摘要： In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell. However, during erase, very efficient tunneling occurs from the floating gate to the substrate and the threshold voltage level decreases to a negative value. The difference between positive and negative values of the threshold voltage is comparable to that of conventional memory cells.

摘要翻译： 在依赖于通过薄氧化层的隧穿作用以在浮动栅极上存储电荷的类型的EEPROM存储器单元中，浮置栅极和存储单元的沟道区域被提供与衬底中相同类型的额外掺杂 以便将存储器单元的处女状态阈值电压提高到高的正值，例如4伏特。 此外，控制栅极和浮置栅极之间的重叠区域减小到在编程期间浮置栅极和控制栅极之间的电容基本上等于浮置栅极和衬底之间的电容，但是在编程期间的有效电容 在擦除模式期间浮动栅极和衬底大大减小。 结果，在编程期间很少或没有隧道发生，并且阈值电压电平与存储器单元的处女阈值相同。 然而，在擦除期间，从浮置栅极到衬底发生非常有效的隧穿，并且阈值电压电平降低到负值。 阈值电压的正值和负值之间的差异与常规存储器单元的差值相当。

公开(公告)号：US4527255A

公开(公告)日：1985-07-02

申请号：US395531

申请日：1982-07-06

申请人： Parviz Keshtbod

发明人： Parviz Keshtbod

IPC分类号： G11C14/00 ,  G11C11/40

CPC分类号： G11C14/00 ,  Y10S257/904

摘要： A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

摘要翻译： 非易失性存储单元（20）包含一对交叉耦合的类似极性FET（Q1和Q2），其用作用于存储数据位和类似极性的可变阈值绝缘栅的易失性位置（​​21） 用作非易失性存储位置（22）的FET（Q3）。 可变阈值FET的源极耦合到交叉耦合FET中的一个的漏极，其绝缘栅电极耦合到交叉耦合FET的另一个的漏极，其漏极耦合到电源。 一对阻抗元件（R1和R2）分别耦合在交叉耦合FET的漏极之间，另一方面则耦合在电源上。 在电源关闭之前，导致数据位蒸发，电源被脉冲到适当的电平，以使该位被传送到非易失性位置。 当电源恢复到正常电平时，原始数据位自动返回到易失性位置。