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公开(公告)号：US20060198210A1
公开(公告)日：2006-09-07
申请号：US11401261
申请日：2006-04-11
IPC分类号： G11C7/06
CPC分类号： G11C15/04 , G11C15/043
摘要： A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using the same current path as that for a search operation, thereby providing a highly integrated array without reducing the original search speed. A rewrite data line is provided in parallel with a match line, and rewrite transistors are inserted between the rewrite data line and the storage nodes within each dynamic CAM cell. With this cell configuration, the data stored at each storage node is read out to the match line one at a time and rewritten through the rewrite data line to carry out a refresh operation.
摘要翻译： 提供由三元动态CAM单元组成的T-CAM阵列，每个三角形动态CAM单元包括多个晶体管。 在使用与搜索操作相同的当前路径的同时读取存储的数据到匹配行时，可以执行刷新操作，从而提供高度集成的阵列而不降低原始搜索速度。 与匹配线并行提供重写数据线，并且在每个动态CAM单元内的重写数据线和存储节点之间插入重写晶体管。 利用该单元配置，将存储在每个存储节点处的数据一次读出到匹配行，并通过重写数据行重写以执行刷新操作。
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公开(公告)号：US20100072451A1
公开(公告)日：2010-03-25
申请号：US12373185
申请日：2006-07-21
申请人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
发明人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.
摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。
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公开(公告)号：US20120249180A1
公开(公告)日：2012-10-04
申请号：US13429056
申请日：2012-03-23
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.
摘要翻译： 本文公开了一种可用于电平移位电路的装置。 该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路， 第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管 电源线，使第五晶体管不导通以使第一反相器停用;以及控制电路，被配置为在第一反相器停用期间防止输出端子进入电浮动状态。
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94.发明申请SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF 审中-公开具有开放式线型存储器单元阵列的半导体存储器件及其控制方法公开(公告)号：US20110176379A1
公开(公告)日：2011-07-21
申请号：US13008408
申请日：2011-01-18
申请人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
发明人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.
摘要翻译： 半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。 写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位 在第二位线的数据写入时的第二本地数据线。
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公开(公告)号：US20090086551A1
公开(公告)日：2009-04-02
申请号：US12285204
申请日：2008-09-30
CPC分类号： G11C11/4093 , G06F11/1004 , G11C7/1006 , G11C7/1012 , G11C8/12
摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.
摘要翻译： 公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组 第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚 。
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公开(公告)号：US20070153617A1
公开(公告)日：2007-07-05
申请号：US11652012
申请日：2007-01-11
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C7/02
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.
摘要翻译： 采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。 当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。 当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。 由于从读数导出的阵列噪声减小，因此边缘被增强。 另外，DRAM的存取时间也减少了。
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公开(公告)号：US06917552B2
公开(公告)日：2005-07-12
申请号：US10671464
申请日：2003-09-29
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C11/4097
摘要： Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.
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公开(公告)号：US20050146960A1
公开(公告)日：2005-07-07
申请号：US11048915
申请日：2005-02-03
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/409 , G11C11/4096 , G11C15/00
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.
摘要翻译： 采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。 当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。 当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。 由于从读数导出的阵列噪声减小，因此边缘被增强。 另外，DRAM的存取时间也减少了。
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公开(公告)号：US08638121B2
公开(公告)日：2014-01-28
申请号：US13429056
申请日：2012-03-23
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.
摘要翻译： 本文公开了一种可用于电平移位电路的装置。 该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路， 第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管 所述第一晶体管被导通以使所述第一反相器无效;以及控制电路，被配置为在所述第一反相器的停用期间防止所述输出端子进入电浮动状态。
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公开(公告)号：US07706208B2
公开(公告)日：2010-04-27
申请号：US12354549
申请日：2009-01-15
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C5/025 , G11C5/04 , G11C7/18 , G11C11/4097 , H01L25/0657 , H01L27/0207 , H01L27/10814 , H01L2224/4826 , H01L2924/13091 , H01L2924/00
摘要： If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of a 1:2 shape. In addition, such conventional layout of memory cell blocks to form the 1:2 shape causes the area of a peripheral circuit region to be limited by the memory blocks, pads to be arranged collectively in the central section of the chip, and wiring to become dense during the enclosure of the chip in the package.In this invention, therefore, four memory blocks, BANK0, BANK1, BANK2, BANK3, BANK3, are constructed into an L shape and then these memory blocks are properly combined and arranged to construct a chip of nearly a 1:2 shape in terms of aspect ratio.
摘要翻译： 如果通过使用纵横比为1:2的存储单元，以常规方式布置存储单元块以创建具有2的奇数功率的容量的存储芯片，则芯片将采取1：1的形状并变得难以 以1：2的形状包装。 此外，存储单元块的这种传统布局形成1：2形状会导致外围电路区域的区域受到存储块的限制，焊盘将被集中布置在芯片的中心部分中，并且布线成为 密封在芯片封装中的封装。 因此，在本发明中，将四个存储块BANK0，BANK1，BANK2，BANK3，BANK3构造成L形，然后将这些存储块适当地组合并布置成构成近似1：2形状的芯片 长宽比。
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